Lines Matching defs:SP
57 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
85 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
119 Reg = SP::I0 + Offset/8;
122 Reg = SP::D0 + Offset/8;
125 Reg = SP::F1 + Offset/4;
128 Reg = SP::Q0 + Offset/16;
157 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
164 unsigned Reg = SP::I0 + Offset/8;
187 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum");
188 if (Reg >= SP::I0 && Reg <= SP::I7)
189 return Reg - SP::I0 + SP::O0;
271 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
273 RetOps.push_back(DAG.getRegister(SP::I0, PtrVT));
426 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
443 &SP::IntRegsRegClass);
456 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
540 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
550 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
568 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
689 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
829 // store SRet argument in %sp+64
830 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
847 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
884 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
894 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
925 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
1081 unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1088 unsigned IReg = SP::I0 + Offset/8;
1141 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1188 unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1190 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1196 // Store to %sp+BIAS+128+Offset
1238 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1240 // %sp+BIAS+128 in ours.
1438 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1439 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1440 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1441 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1443 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1447 addRegisterClass(MVT::v2i32, &SP::IntPairRegClass);
1681 setStackPointerRegisterToSaveRestore(SP::O6);
2001 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
2011 Ops.push_back(DAG.getRegister(SP::O0, PtrVT));
2022 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag);
2055 DAG.getRegister(SP::G7, PtrVT), Offset,
2068 DAG.getRegister(SP::G7, PtrVT), Offset);
2476 DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(SP::I6, PtrVT),
2514 unsigned SPReg = SP::O6;
2515 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
2516 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
2517 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
2545 unsigned FrameReg = SP::I6;
2603 unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT));
2634 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2636 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2643 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
2645 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
2679 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
2680 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
2718 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
2719 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
2793 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
2795 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
2804 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
2806 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
2983 case SP::SELECT_CC_Int_ICC:
2984 case SP::SELECT_CC_FP_ICC:
2985 case SP::SELECT_CC_DFP_ICC:
2986 case SP::SELECT_CC_QFP_ICC:
2987 return expandSelectCC(MI, BB, SP::BCOND);
2988 case SP::SELECT_CC_Int_FCC:
2989 case SP::SELECT_CC_FP_FCC:
2990 case SP::SELECT_CC_DFP_FCC:
2991 case SP::SELECT_CC_QFP_FCC:
2992 return expandSelectCC(MI, BB, SP::FBCOND);
2994 case SP::ATOMIC_LOAD_ADD_32:
2995 return expandAtomicRMW(MI, BB, SP::ADDrr);
2996 case SP::ATOMIC_LOAD_ADD_64:
2997 return expandAtomicRMW(MI, BB, SP::ADDXrr);
2998 case SP::ATOMIC_LOAD_SUB_32:
2999 return expandAtomicRMW(MI, BB, SP::SUBrr);
3000 case SP::ATOMIC_LOAD_SUB_64:
3001 return expandAtomicRMW(MI, BB, SP::SUBXrr);
3002 case SP::ATOMIC_LOAD_AND_32:
3003 return expandAtomicRMW(MI, BB, SP::ANDrr);
3004 case SP::ATOMIC_LOAD_AND_64:
3005 return expandAtomicRMW(MI, BB, SP::ANDXrr);
3006 case SP::ATOMIC_LOAD_OR_32:
3007 return expandAtomicRMW(MI, BB, SP::ORrr);
3008 case SP::ATOMIC_LOAD_OR_64:
3009 return expandAtomicRMW(MI, BB, SP::ORXrr);
3010 case SP::ATOMIC_LOAD_XOR_32:
3011 return expandAtomicRMW(MI, BB, SP::XORrr);
3012 case SP::ATOMIC_LOAD_XOR_64:
3013 return expandAtomicRMW(MI, BB, SP::XORXrr);
3014 case SP::ATOMIC_LOAD_NAND_32:
3015 return expandAtomicRMW(MI, BB, SP::ANDrr);
3016 case SP::ATOMIC_LOAD_NAND_64:
3017 return expandAtomicRMW(MI, BB, SP::ANDXrr);
3019 case SP::ATOMIC_SWAP_64:
3022 case SP::ATOMIC_LOAD_MAX_32:
3023 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_G);
3024 case SP::ATOMIC_LOAD_MAX_64:
3025 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_G);
3026 case SP::ATOMIC_LOAD_MIN_32:
3027 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LE);
3028 case SP::ATOMIC_LOAD_MIN_64:
3029 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LE);
3030 case SP::ATOMIC_LOAD_UMAX_32:
3031 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_GU);
3032 case SP::ATOMIC_LOAD_UMAX_64:
3033 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_GU);
3034 case SP::ATOMIC_LOAD_UMIN_32:
3035 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LEU);
3036 case SP::ATOMIC_LOAD_UMIN_64:
3037 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LEU);
3092 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
3130 bool is64Bit = SP::I64RegsRegClass.hasSubClassEq(MRI.getRegClass(DestReg));
3132 is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
3135 BuildMI(*MBB, MI, DL, TII.get(is64Bit ? SP::LDXri : SP::LDri), Val0Reg)
3162 BuildMI(LoopMBB, DL, TII.get(SP::PHI), ValReg)
3169 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(Rs2Reg);
3177 if (MI->getOpcode() == SP::ATOMIC_LOAD_NAND_32 ||
3178 MI->getOpcode() == SP::ATOMIC_LOAD_NAND_64) {
3181 BuildMI(LoopMBB, DL, TII.get(SP::XORri), UpdReg).addReg(TmpReg).addImm(-1);
3184 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg)
3187 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg);
3188 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND))
3282 return std::make_pair(0U, &SP::IntPairRegClass);
3284 return std::make_pair(0U, &SP::IntRegsRegClass);
