Lines Matching refs:BaseReg
266 unsigned BaseReg, IndexReg, TmpReg, Scale;
276 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
280 unsigned getBaseReg() { return BaseReg; }
384 // If we already have a BaseReg, then assume this is the IndexReg with
386 if (!BaseReg) {
387 BaseReg = TmpReg;
389 assert (!IndexReg && "BaseReg/IndexReg already set!");
421 // If we already have a BaseReg, then assume this is the IndexReg with
423 if (!BaseReg) {
424 BaseReg = TmpReg;
426 assert (!IndexReg && "BaseReg/IndexReg already set!");
600 // If we already have a BaseReg, then assume this is the IndexReg with
602 if (!BaseReg) {
603 BaseReg = TmpReg;
605 assert (!IndexReg && "BaseReg/IndexReg already set!");
713 CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
833 static bool CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg,
838 if (BaseReg != 0 && IndexReg != 0) {
839 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
846 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
853 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {
859 if (((BaseReg == X86::BX || BaseReg == X86::BP) &&
861 ((BaseReg == X86::SI || BaseReg == X86::DI) &&
879 unsigned diReg = Op1.Mem.BaseReg;
880 unsigned siReg = Op2.Mem.BaseReg;
1012 unsigned basereg =
1016 /*BaseReg=*/basereg, /*IndexReg=*/0, /*Scale=*/1,
1021 unsigned basereg =
1025 /*BaseReg=*/basereg, /*IndexReg=*/0, /*Scale=*/1,
1068 unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,
1105 BaseReg = BaseReg ? BaseReg : 1;
1106 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
1121 // bracketed expression (i.e., ImmDisp [ BaseReg + Scale*IndexReg + Disp])
1302 // Parse [ Symbol + ImmDisp ] and [ BaseReg + Scale*IndexReg + ImmDisp ]. We
1340 int BaseReg = SM.getBaseReg();
1345 if (!BaseReg && !IndexReg) {
1352 if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {
1356 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
1361 return CreateMemForInlineAsm(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1439 /*BaseReg=*/0, /*IndexReg=*/0, /*Scale=*/1,
1461 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0,/*IndexReg=*/0,
1510 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1530 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0, /*IndexReg=*/0,
1555 // BaseReg is non-zero to avoid assertions. In the context of inline asm,
1559 /*BaseReg=*/1, /*IndexReg=*/0, /*Scale=*/1,
1748 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1894 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
1955 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
1961 if (ParseRegister(BaseReg, StartLoc, EndLoc)) return nullptr;
1962 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
2003 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
2042 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
2043 (is64BitMode() || (BaseReg != X86::BX && BaseReg != X86::BP &&
2044 BaseReg != X86::SI && BaseReg != X86::DI)) &&
2045 BaseReg != X86::DX) {
2049 if (BaseReg == 0 &&
2056 if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {
2061 if (SegReg || BaseReg || IndexReg)
2062 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
2256 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2258 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
2268 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2270 Operands[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
