Lines Matching refs:BaseReg
60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
64 if (is16BitMode(STI) && BaseReg.getReg() == 0 &&
67 if ((BaseReg.getReg() != 0 &&
68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
226 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
229 if ((BaseReg.getReg() != 0 &&
230 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
241 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
244 if ((BaseReg.getReg() != 0 &&
245 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
372 unsigned BaseReg = Base.getReg();
376 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
401 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
406 if (BaseReg) {
454 // There is no BaseReg; this is the plain [disp16] case.
464 // If no BaseReg, issue a RIP relative instruction only if the MCE can
476 (!is64BitMode(STI) || BaseReg != 0)) {
478 if (BaseReg == 0) { // [disp32] in X86-32 mode
526 if (BaseReg == 0) {
559 if (BaseReg == 0) {
