Lines Matching refs:CC1
14409 unsigned CC0, CC1;
14412 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14415 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14421 DAG.getConstant(CC1, dl, MVT::i8));
21462 // (CMOV (CMOV F, T, cc1), T, cc2)
24613 X86::CondCode &CC1, SDValue &Flags,
24645 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24820 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24821 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24838 X86::CondCode CC0, CC1;
24840 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24844 CC1 = X86::GetOppositeBranchCondition(CC1);
24850 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
25159 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
25161 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
25163 cc0 = cc1;
25164 cc1 = tmp;
25167 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
25168 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
