Lines Matching refs:Left
276 // (low) operations are left as Legal, as there are single-result
6411 // Is it a vector logical left shift?
7285 /// specified as a *right shift* because x86 is little-endian, it is a *left
7404 /// matches elements from one of the input vectors shuffled to the left or
7409 /// PSHL : (little-endian) left bit shift.
7415 /// PSLLDQ : (little-endian) left byte shift
7431 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7434 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7440 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7442 unsigned Pos = Left ? i + Shift : i;
7443 unsigned Low = Left ? i : i + Shift;
7452 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7480 for (bool Left : {true, false})
7481 if (CheckZeros(Shift, Scale, Left))
7483 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
8027 // shift left. We know that we can do a vector shift left because all
11773 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
13730 // 1 node left, i.e. the final OR'd value of all vectors.
13845 // leads to the ADD being left around and reselected, with the result being
18204 // step to the left):
18578 // +ve/-ve Amt = shift left/right.
19029 // +ve/-ve Amt = rotate left/right.
19443 // The only element type left is i16.
19447 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
21138 // Check if there is enough room left to pull this argument.
24272 // left side invert the predicate to simplify logic below.
25275 // The Left side has to be a trunc.
25843 // Check if each element of the vector is left-shifted by one.
26608 // Shift left by 16 bits, then arithmetic-shift right by 16 bits.
