Lines Matching refs:ResVT
4190 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4192 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4195 return (Index == 0 || Index == ResVT.getVectorNumElements());
6616 MVT ResVT = Op.getSimpleValueType();
6618 assert((ResVT.is256BitVector() ||
6619 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6623 unsigned NumElems = ResVT.getVectorNumElements();
6624 if (ResVT.is256BitVector())
6625 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6628 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6629 ResVT.getVectorNumElements()/2);
6633 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6635 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6642 MVT ResVT = Op.getSimpleValueType();
6648 SDValue Undef = DAG.getUNDEF(ResVT);
6664 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef,
6668 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6669 ResVT.getVectorNumElements()/2);
6678 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6684 unsigned NumElems = ResVT.getVectorNumElements();
6689 if (ResVT.getSizeInBits() >= 16)
6694 SDValue ZeroVec = getZeroVector(ResVT, Subtarget, DAG, dl);
6700 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6702 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V1, ZeroIdx);
6706 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, IdxVal);
6709 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V2, IdxVal);
6711 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6712 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, V1, V2, IdxVal);
11881 MVT ResVT = Op.getSimpleValueType();
11885 if (ResVT.is128BitVector() &&
11890 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
