Lines Matching refs:TLI
5091 const TargetLowering &TLI) {
5161 const TargetLowering &TLI) {
5190 const TargetLowering &TLI) {
5296 const TargetLowering &TLI, SDLoc dl) {
5301 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5617 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5619 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5695 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5696 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
11936 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11937 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
13523 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13524 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13549 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13587 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13971 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13972 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
15265 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15291 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15330 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15336 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15366 assert(TLI.isTypeLegal(WideVecVT) &&
15372 TLI.getPointerTy(DAG.getDataLayout()));
15410 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15758 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15759 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16244 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16245 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
17882 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17893 TLI.isOperationLegal(ISD::CTLZ, VT)) {
19718 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19720 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19730 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
20163 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20267 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
23525 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23526 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
23531 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
23536 if (TLI.isTypeLegal(VT) && Subtarget->hasFp256() && VT.is256BitVector() &&
23562 TLI.isOperationLegal(Opcode, VT)) {
23698 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23702 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23854 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23857 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23886 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23952 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23953 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23969 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23978 (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
24261 if (!TLI.isTypeLegal(VT))
24339 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
24414 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
24435 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
25292 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25294 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
25908 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25918 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25926 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
26048 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26054 if (TLI.isTruncStoreLegal(VT, StVT))
26129 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26137 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
26147 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
26175 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26185 if (TLI.isTruncStoreLegal(VT, StVT))
26210 if (!TLI.isTypeLegal(WideVecVT))
26222 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
26227 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
26238 TLI.getPointerTy(DAG.getDataLayout()));
26900 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26902 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
27435 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
27445 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
