Lines Matching refs:getOpcode
2328 if (Copy->getOpcode() == ISD::CopyToReg) {
2334 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2340 if (UI->getOpcode() != X86ISD::RET_FLAG)
3390 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3623 if (Arg.getOpcode() == ISD::CopyFromReg) {
3634 unsigned Opcode = Def->getOpcode();
3656 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
4172 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4444 if (Vec.getOpcode() == ISD::UNDEF)
4456 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4490 if (Vec.getOpcode() == ISD::UNDEF)
4524 Result.getOpcode() != ISD::UNDEF) {
4748 switch(N->getOpcode()) {
4797 while (MaskNode->getOpcode() == ISD::BITCAST)
4800 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4813 if (Op->getOpcode() == ISD::UNDEF) {
4840 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4841 Ptr->getOpcode() == X86ISD::WrapperRIP)
4895 while (MaskNode->getOpcode() == ISD::BITCAST)
4900 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4908 if (Op->getOpcode() == ISD::UNDEF)
4919 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4938 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4939 Ptr->getOpcode() == X86ISD::WrapperRIP)
4958 while (MaskNode->getOpcode() == ISD::BITCAST)
4961 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4972 if (Op->getOpcode() == ISD::UNDEF)
4991 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4992 Ptr->getOpcode() == X86ISD::WrapperRIP)
5031 unsigned Opcode = V.getOpcode();
5076 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5080 if (V.getOpcode() == ISD::BUILD_VECTOR)
5195 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5208 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5404 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5407 getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5410 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5416 if (Elt.getOpcode() == ISD::UNDEF)
5518 switch (Op.getOpcode()) {
5534 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5535 Ld.getOpcode() == ISD::ConstantFP);
5553 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5554 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5566 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5567 Ld.getOpcode() == ISD::ConstantFP);
5708 unsigned Opc = Op.getOperand(i).getOpcode();
5770 if (In.getOpcode() != ISD::UNDEF)
5816 if (In.getOpcode() == ISD::UNDEF)
5900 if (Op->getOpcode() == ISD::UNDEF) {
5908 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5918 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5919 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5930 if (V0.getOpcode() == ISD::UNDEF) {
5936 if (V1.getOpcode() == ISD::UNDEF) {
6012 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6014 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6018 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6019 V1_LO->getOpcode() != ISD::UNDEF))
6022 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6023 V1_HI->getOpcode() != ISD::UNDEF))
6060 unsigned Opcode = Op.getOpcode();
6076 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6077 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6094 if (InVec0.getOpcode() == ISD::UNDEF) {
6099 if (InVec1.getOpcode() == ISD::UNDEF) {
6126 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6127 InVec1.getOpcode() != ISD::UNDEF)
6145 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6149 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6184 ((InVec0.getOpcode() == ISD::UNDEF ||
6185 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6186 ((InVec1.getOpcode() == ISD::UNDEF ||
6187 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6192 ((InVec0.getOpcode() == ISD::UNDEF ||
6193 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6194 ((InVec1.getOpcode() == ISD::UNDEF ||
6195 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6205 ((InVec0.getOpcode() == ISD::UNDEF ||
6206 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6207 ((InVec1.getOpcode() == ISD::UNDEF ||
6208 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6212 ((InVec0.getOpcode() == ISD::UNDEF ||
6213 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6214 ((InVec1.getOpcode() == ISD::UNDEF ||
6215 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6320 if (Elt.getOpcode() == ISD::UNDEF)
6323 if (Elt.getOpcode() != ISD::Constant &&
6324 Elt.getOpcode() != ISD::ConstantFP)
6564 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6570 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6581 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6599 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6894 while (V1.getOpcode() == ISD::BITCAST)
6896 while (V2.getOpcode() == ISD::BITCAST)
6913 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6919 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7912 while (V.getOpcode() == ISD::BITCAST)
7920 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7921 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7937 while (V.getOpcode() == ISD::BITCAST)
8077 const unsigned V0Opc = V0.getOpcode();
8129 switch (V.getOpcode()) {
8163 if (V.getOpcode() == ISD::BITCAST && VT.isInteger())
8169 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8170 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8521 while (V.getOpcode() == ISD::BITCAST)
8524 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
9979 while (V.getOpcode() == ISD::BITCAST)
11252 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11253 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11526 if ((User->getOpcode() != ISD::STORE ||
11528 (User->getOpcode() != ISD::BITCAST ||
11719 if (Vec.getOpcode() == ISD::UNDEF)
11923 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11929 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
12464 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12478 if (Op.getOpcode() == ISD::SHL_PARTS) {
12499 if (Op.getOpcode() == ISD::SHL_PARTS) {
13194 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13472 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13475 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13481 if (User->getOpcode() == ISD::FNEG)
13532 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13651 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13675 if (I->getOpcode() == ISD::OR) {
13684 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13746 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13752 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13753 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13784 switch (Op->getOpcode()) {
13819 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13823 switch (Arith.getOpcode()) {
13839 switch (ArithOp.getOpcode()) {
13853 if (UI->getOpcode() != ISD::CopyToReg &&
13854 UI->getOpcode() != ISD::SETCC &&
13855 UI->getOpcode() != ISD::STORE)
13891 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13916 if (UI->getOpcode() == ISD::STORE)
13920 switch (ArithOp.getOpcode()) {
13961 switch (WideVal.getOpcode()) {
13972 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14032 Cmp.getOpcode() != X86ISD::CMP ||
14133 if (Op0.getOpcode() == ISD::TRUNCATE)
14135 if (Op1.getOpcode() == ISD::TRUNCATE)
14139 if (Op1.getOpcode() == ISD::SHL)
14141 if (Op0.getOpcode() == ISD::SHL) {
14156 } else if (Op1.getOpcode() == ISD::Constant) {
14161 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14247 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14268 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14269 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14700 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14717 if (Op0.getOpcode() == X86ISD::SETCC) {
14763 assert(Carry.getOpcode() != ISD::CARRY_FALSE);
14772 unsigned Opc = Op.getNode()->getOpcode();
14797 if (V.getOpcode() != ISD::TRUNCATE)
14818 if (Cond.getOpcode() == ISD::SETCC &&
14878 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14883 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14908 if (Cond.getOpcode() == ISD::SETCC) {
14918 if (Cond.getOpcode() == X86ISD::SETCC &&
14919 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14964 if (Cond.getOpcode() == ISD::AND &&
14965 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
14971 unsigned CondOpcode = Cond.getOpcode();
14977 unsigned Opc = Cmp.getOpcode();
15032 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15050 if (Cond.getOpcode() == X86ISD::SUB) {
15070 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15074 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15119 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15120 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15436 Opc = Op.getOpcode();
15439 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15441 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15448 if (Op.getOpcode() != ISD::XOR)
15451 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15465 if (Cond.getOpcode() == ISD::SETCC) {
15470 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15471 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15472 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15473 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15474 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15475 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15486 else if (Cond.getOpcode() == X86ISD::ADD ||
15487 Cond.getOpcode() == X86ISD::SUB ||
15488 Cond.getOpcode() == X86ISD::SMUL ||
15489 Cond.getOpcode() == X86ISD::UMUL)
15494 if (Cond.getOpcode() == ISD::AND &&
15495 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
15501 unsigned CondOpcode = Cond.getOpcode();
15507 unsigned Opc = Cmp.getOpcode();
15525 CondOpcode = Cond.getOpcode();
15608 if (User->getOpcode() == ISD::BR) {
15637 } else if (Cond.getOpcode() == ISD::SETCC &&
15649 if (User->getOpcode() == ISD::BR) {
15668 } else if (Cond.getOpcode() == ISD::SETCC &&
15680 if (User->getOpcode() == ISD::BR) {
15709 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16005 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16017 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16029 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16070 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16162 switch (Op.getOpcode()) {
16181 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16205 if (Op.getOpcode() == X86ISD::FSETCC)
16207 if (Op.getOpcode() == X86ISD::VFPCLASS ||
16208 Op.getOpcode() == X86ISD::VFPCLASSS)
16211 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16975 if (Src.getOpcode() == ISD::UNDEF)
17787 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17788 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17892 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17905 assert(Op.getOpcode() == ISD::CTTZ &&
17947 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17948 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18140 switch (Op->getOpcode()) {
18214 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18313 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18314 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18353 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18358 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18366 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18370 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18379 if (Op.getOpcode() == ISD::SHL) {
18390 if (Op.getOpcode() == ISD::SRL) {
18401 if (Op.getOpcode() == ISD::SRA) {
18431 if (Amt.getOpcode() != ISD::BITCAST ||
18432 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18465 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18468 if (Op.getOpcode() == ISD::SRA)
18482 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18483 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18485 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18486 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18488 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18496 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18499 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18506 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18510 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18538 Amt.getOpcode() == ISD::BITCAST &&
18539 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18552 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18574 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18582 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18586 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18588 if (Op.getOpcode() == ISD::SRA)
18594 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18598 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18599 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18607 Op.getOpcode() == ISD::SRA) {
18619 if (Op.getOpcode() == ISD::SHL &&
18631 if (Op->getOpcode() == ISD::UNDEF) {
18650 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18719 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18722 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18739 unsigned Opc = Op.getOpcode();
18783 unsigned ShiftOpcode = Op->getOpcode();
18810 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18832 if (Op->getOpcode() == ISD::SRA) {
18894 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18898 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18912 getOpcode(), dl, ExtVT, RLo, ALo);
18913 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18920 unsigned ShiftOpcode = Op->getOpcode();
18992 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
19007 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
19008 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
19026 assert((Op.getOpcode() == ISD::ROTL) && "Only ROTL supported");
19062 switch (Op.getOpcode()) {
19677 switch (Op.getOpcode()) {
19768 if (InOp.getOpcode() == ISD::CONCAT_VECTORS &&
20054 switch (Op.getOpcode()) {
20164 switch (N->getOpcode()) {
20209 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
20231 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
20773 if (Val.getOpcode() != ISD::LOAD)
20915 switch (MI->getOpcode()) {
20952 switch (MI->getOpcode()) {
21378 switch (MI->getOpcode()) {
21554 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21694 switch (MI->getOpcode()) {
22231 switch (MI->getOpcode()) {
22286 switch (MI->getOpcode()) {
22378 switch (MI->getOpcode()) {
22525 unsigned Opc = Op.getOpcode();
22591 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22603 if (N->getOpcode() == X86ISD::Wrapper) {
22656 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22657 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22668 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22669 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22670 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22758 while (Input.getOpcode() == ISD::BITCAST)
22813 if (Depth == 1 && Root->getOpcode() == Shuffle)
22831 if (Depth == 1 && Root->getOpcode() == Shuffle)
22845 if (Depth == 1 && Root->getOpcode() == Shuffle)
22868 if (Depth == 1 && Root->getOpcode() == Shuffle)
22971 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22983 if (!isTargetShuffle(Op.getOpcode()))
23036 switch (Op.getOpcode()) {
23101 switch (N.getOpcode()) {
23126 assert(N.getOpcode() == X86ISD::PSHUFD &&
23136 switch (V.getOpcode()) {
23179 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
23186 switch (V.getOpcode()) {
23192 if (V.getOpcode() == CombineOp)
23218 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
23228 switch (W.getOpcode()) {
23234 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
23240 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
23261 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
23264 unsigned CombineOpcode = N.getOpcode();
23269 switch (V.getOpcode()) {
23280 if (V.getOpcode() == CombineOpcode)
23306 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
23327 switch (N.getOpcode()) {
23354 if (Op0.getOpcode() == ISD::UNDEF &&
23355 Op1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE) {
23379 switch (N.getOpcode()) {
23394 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
23410 (V.getOpcode() == X86ISD::PSHUFLW ||
23411 V.getOpcode() == X86ISD::PSHUFHW) &&
23412 V.getOpcode() != N.getOpcode() &&
23415 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
23417 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
23420 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23421 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23469 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
23482 if (V1.getOpcode() == ISD::FADD && V2.getOpcode() == ISD::FSUB) {
23485 } else if (V1.getOpcode() != ISD::FSUB || V2.getOpcode() != ISD::FADD)
23537 N->getOpcode() == ISD::VECTOR_SHUFFLE)
23553 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
23554 N0.getOpcode() == ISD::BITCAST) {
23557 unsigned Opcode = BC0.getOpcode();
23585 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
23601 if (isTargetShuffle(N->getOpcode())) {
23640 if (InVec.getOpcode() == ISD::BITCAST) {
23653 if (!isTargetShuffle(InVec.getOpcode()))
23677 if (LdNode.getOpcode() == ISD::BITCAST) {
23729 if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
23744 switch (N0.getOpcode()) {
23753 N0.getOperand(0).getOpcode() == ISD::BITCAST &&
23776 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23788 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23791 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23802 InputVector.getOpcode() == ISD::BITCAST &&
23827 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23834 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23835 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23922 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23924 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23946 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23976 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
24132 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
24147 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
24148 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
24244 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
24265 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
24290 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
24300 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
24312 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
24326 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
24337 Cond.getOpcode() == ISD::SETCC &&
24383 if ((N->getOpcode() == ISD::VSELECT ||
24384 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
24395 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
24449 if (I->getOpcode() != ISD::VSELECT)
24496 if (Cmp.getOpcode() != X86ISD::CMP &&
24497 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
24530 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
24531 SetCC.getOpcode() == ISD::TRUNCATE ||
24532 SetCC.getOpcode() == ISD::AND) {
24533 if (SetCC.getOpcode() == ISD::AND) {
24547 switch (SetCC.getOpcode()) {
24575 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
24576 Op.getOpcode() == ISD::TRUNCATE)
24580 if ((Op.getOpcode() != X86ISD::RDRAND &&
24581 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
24615 if (Cond->getOpcode() == X86ISD::CMP) {
24625 switch (Cond->getOpcode()) {
24639 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24640 SetCC1.getOpcode() != X86ISD::SETCC ||
24666 switch (Cond.getOpcode()) {
24800 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24902 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24958 N1C && N0.getOpcode() == ISD::AND &&
24959 N0.getOperand(1).getOpcode() == ISD::Constant) {
24976 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24978 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24979 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24981 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24982 N00.getOpcode() == ISD::ANY_EXTEND) &&
24983 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
25026 if (!VT.isInteger() || VT.isVector() || N1.getOpcode() != ISD::Constant ||
25027 N0.getOpcode() != ISD::SHL || !N0.hasOneUse() ||
25028 N0.getOperand(1).getOpcode() != ISD::Constant)
25097 if (N->getOpcode() == ISD::SHL)
25101 if (N->getOpcode() == ISD::SRA)
25106 if (N->getOpcode() != ISD::SRA)
25131 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
25143 switch (UI->getOpcode()) {
25226 if (N->getOpcode() == ISD::BITCAST)
25232 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
25236 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
25237 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
25257 assert((N->getOpcode() == ISD::ANY_EXTEND ||
25258 N->getOpcode() == ISD::ZERO_EXTEND ||
25259 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
25266 if (Narrow->getOpcode() != ISD::XOR &&
25267 Narrow->getOpcode() != ISD::AND &&
25268 Narrow->getOpcode() != ISD::OR)
25276 if (N0.getOpcode() != ISD::TRUNCATE)
25285 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
25294 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
25309 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
25310 unsigned Opcode = N->getOpcode();
25341 if (N0.getOpcode() != ISD::BITCAST ||
25342 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
25347 if (N1.getOpcode() == ISD::BITCAST)
25349 if (N1.getOpcode() != ISD::BUILD_VECTOR)
25357 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
25425 if (N->getOpcode() == ISD::AND)
25427 else if (N->getOpcode() == ISD::OR)
25429 else if (N->getOpcode() == ISD::XOR)
25439 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
25479 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
25506 if (N0.getOpcode() == ISD::XOR &&
25512 if (N1.getOpcode() == ISD::XOR &&
25543 if (N0.getOpcode() == X86ISD::ANDNP)
25546 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
25561 if (Mask.getOpcode() == ISD::BITCAST)
25563 if (X.getOpcode() == ISD::BITCAST)
25565 if (Y.getOpcode() == ISD::BITCAST)
25575 if (Mask.getOpcode() == ISD::SRA) {
25579 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
25591 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
25627 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
25629 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
25640 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
25642 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
25649 if (ShAmt0.getOpcode() == ISD::SUB) {
25656 if (ShAmt1.getOpcode() == ISD::SUB) {
25660 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
25696 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25697 N0.getOpcode() == ISD::ADD &&
25699 N1.getOpcode() == ISD::SRA &&
25728 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25737 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25823 if (In.getOpcode() != ISD::SRL)
25848 if (LHS.getOpcode() != ISD::ADD)
25859 Operands[0].getOpcode() == ISD::ZERO_EXTEND &&
25872 if (Operands[0].getOpcode() == ISD::ADD)
25874 else if (Operands[1].getOpcode() != ISD::ADD)
25888 if (Operands[j].getOpcode() != ISD::ZERO_EXTEND ||
25982 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
26285 ChainVal->getOpcode() == ISD::TokenFactor) {
26371 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
26413 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
26414 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
26439 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26440 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
26442 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
26447 if (LHS.getOpcode() != ISD::UNDEF)
26457 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26458 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
26460 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
26465 if (RHS.getOpcode() != ISD::UNDEF)
26715 if (Arg.getOpcode() == ISD::FMUL && (SVT == MVT::f32 || SVT == MVT::f64) &&
26725 switch (Arg.getOpcode()) {
26756 switch (N->getOpcode()) {
26771 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
26788 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
26797 switch (N->getOpcode()) {
26910 if (Op.getOpcode() == ISD::BITCAST)
26913 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
26937 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
26938 N0.getOpcode() == ISD::SIGN_EXTEND)) {
26943 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
26969 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
26986 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
27021 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
27124 bool NegA = (A.getOpcode() == ISD::FNEG);
27125 bool NegB = (B.getOpcode() == ISD::FNEG);
27126 bool NegC = (C.getOpcode() == ISD::FNEG);
27157 if (N0.getOpcode() == ISD::AND &&
27161 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
27171 if (N0.getOpcode() == ISD::TRUNCATE &&
27175 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
27191 if (N0.getOpcode() == ISD::UDIVREM &&
27214 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
27221 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
27232 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
27241 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
27297 if (Mask.getOpcode() == ISD::SIGN_EXTEND_INREG) {
27338 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
27397 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
27398 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
27417 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
27479 if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
27533 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
27534 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
27538 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
27546 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
27555 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
27557 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
27561 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
27593 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
27628 while (V.getOpcode() == ISD::BITCAST)
27631 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
27656 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
27657 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
27682 switch (N->getOpcode()) {
27793 switch (Op.getOpcode()) {
27805 if (UI->getOpcode() != ISD::CopyToReg)
28261 } else if (Op.getOpcode() == ISD::ADD) {
28267 } else if (Op.getOpcode() == ISD::SUB) {
