Lines Matching defs:STI
104 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
105 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
107 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
110 Subtarget(STI), RI(STI.getTargetTriple()) {
4495 const X86Subtarget &STI,
4497 if (STI.hasAVX512()) {
4509 bool HasAVX = STI.hasAVX();
4515 if (STI.is64Bit())
4612 const X86Subtarget &STI) {
4613 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
4620 const X86Subtarget &STI) {
4621 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
7178 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
7182 if (STI.is64Bit())
7201 const X86InstrInfo *TII = STI.getInstrInfo();
7204 if (STI.isPICStyleGOT())
7215 if (STI.isPICStyleGOT()) {
7296 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7297 const bool is64Bit = STI.is64Bit();
7298 const X86InstrInfo *TII = STI.getInstrInfo();
7316 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7317 const bool is64Bit = STI.is64Bit();
7318 const X86InstrInfo *TII = STI.getInstrInfo();
