Lines Matching refs:Insn
46 uint64_t &Size, uint16_t &Insn) {
53 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
58 uint64_t &Size, uint32_t &Insn) {
65 Insn =
93 unsigned Insn,
98 unsigned Insn,
103 unsigned Insn,
108 unsigned Insn,
113 unsigned Insn,
118 unsigned Insn,
123 unsigned Insn,
128 unsigned Insn,
133 unsigned Insn,
138 unsigned Insn,
143 unsigned Insn,
148 unsigned Insn,
153 unsigned Insn,
158 unsigned Insn,
163 unsigned Insn,
168 unsigned Insn,
173 unsigned Insn,
178 unsigned Insn,
183 unsigned Insn,
188 unsigned Insn,
193 unsigned Insn,
241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
242 unsigned Combined = fieldFromInstruction(Insn, 6, 5);
245 if (fieldFromInstruction(Insn, 5, 1)) {
253 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
254 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
261 unsigned Combined = fieldFromInstruction(Insn, 6, 5);
268 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
269 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
270 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
275 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
278 unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
282 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
285 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
288 return Decode3RInstruction(Inst, Insn, Address, Decoder);
291 return Decode3RInstruction(Inst, Insn, Address, Decoder);
294 return Decode3RInstruction(Inst, Insn, Address, Decoder);
297 return Decode3RInstruction(Inst, Insn, Address, Decoder);
300 return Decode3RInstruction(Inst, Insn, Address, Decoder);
303 return Decode3RInstruction(Inst, Insn, Address, Decoder);
306 return Decode3RInstruction(Inst, Insn, Address, Decoder);
309 return Decode3RInstruction(Inst, Insn, Address, Decoder);
312 return Decode3RInstruction(Inst, Insn, Address, Decoder);
315 return Decode3RInstruction(Inst, Insn, Address, Decoder);
318 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
321 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
324 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
327 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
330 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
333 return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
336 return Decode3RInstruction(Inst, Insn, Address, Decoder);
339 return Decode3RInstruction(Inst, Insn, Address, Decoder);
345 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
350 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
358 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
363 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
371 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
374 DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
376 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
384 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
387 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
389 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
398 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
401 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
403 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
411 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
414 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
416 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
424 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn
427 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
429 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
438 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
441 unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
442 fieldFromInstruction(Insn, 27, 5) << 4;
446 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
449 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
452 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
455 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
458 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
461 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
464 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
467 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
470 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
473 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
476 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
479 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
482 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
485 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
488 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
491 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
494 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
497 return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
500 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
503 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
509 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
512 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
515 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
523 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
526 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
529 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
537 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
540 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
550 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
553 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
563 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
566 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
576 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
579 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
589 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
593 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
603 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
607 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
618 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
622 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
632 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
636 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
646 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
650 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
653 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
666 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
670 unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
674 return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
680 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
684 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
686 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
687 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
689 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
700 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
703 unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
705 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
719 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
722 unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
724 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
