Lines Matching refs:reg
127 #define GET_CHANNEL_SRC( reg, channel ) ((reg<<(channel*4)) & (0xf<<20))
130 #define GET_UREG_TYPE(reg) (((reg)>>UREG_TYPE_SHIFT)®_TYPE_MASK)
131 #define GET_UREG_NR(reg) (((reg)>>UREG_NR_SHIFT)®_NR_MASK)
140 swizzle(int reg, uint x, uint y, uint z, uint w)
146 return ((reg & ~UREG_XYZW_CHANNEL_MASK) |
147 CHANNEL_SRC(GET_CHANNEL_SRC(reg, x), 0) |
148 CHANNEL_SRC(GET_CHANNEL_SRC(reg, y), 1) |
149 CHANNEL_SRC(GET_CHANNEL_SRC(reg, z), 2) |
150 CHANNEL_SRC(GET_CHANNEL_SRC(reg, w), 3));
154 #define A0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT)
155 #define D0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT)
156 #define T0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT)
157 #define A0_SRC0( reg ) (((reg)&UREG_MASK)>>UREG_A0_SRC0_SHIFT_LEFT)
158 #define A1_SRC0( reg ) (((reg)&UREG_MASK)<<UREG_A1_SRC0_SHIFT_RIGHT)
159 #define A1_SRC1( reg ) (((reg)&UREG_MASK)>>UREG_A1_SRC1_SHIFT_LEFT)
160 #define A2_SRC1( reg ) (((reg)&UREG_MASK)<<UREG_A2_SRC1_SHIFT_RIGHT)
161 #define A2_SRC2( reg ) (((reg)&UREG_MASK)>>UREG_A2_SRC2_SHIFT_LEFT)
165 #define T0_SAMPLER( reg ) (GET_UREG_NR(reg)<<T0_SAMPLER_NR_SHIFT)
166 #define T1_ADDRESS_REG( reg ) ((GET_UREG_NR(reg)<<T1_ADDRESS_REG_NR_SHIFT) | \
167 (GET_UREG_TYPE(reg)<<T1_ADDRESS_REG_TYPE_SHIFT))
