Lines Matching full:surf
1240 struct r600_surface *surf)
1243 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1244 struct pipe_resource *pipe_tex = surf->base.texture;
1245 unsigned level = surf->base.u.tex.level;
1264 surf->base.u.tex.first_layer;
1304 if (util_format_get_blocksize(surf->base.format) >= 16)
1308 desc = util_format_description(surf->base.format);
1344 format = r600_translate_colorformat(surf->base.format);
1347 swap = r600_translate_colorswap(surf->base.format);
1370 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1398 surf->export_16bpc = true;
1408 surf->cb_color_base = (base_offset + offset) >> 8;
1409 surf->cb_color_dim = color_dim;
1410 surf->cb_color_info = color_info;
1411 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1412 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1414 surf->cb_color_view = 0;
1416 surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1417 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1419 surf->cb_color_attrib = color_attrib;
1421 surf->cb_color_fmask = (base_offset + rtex->fmask_offset) >> 8;
1422 surf->cb_color_cmask = (base_offset + rtex->cmask_offset) >> 8;
1424 surf->cb_color_fmask = surf->cb_color_base;
1425 surf->cb_color_cmask = surf->cb_color_base;
1427 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1428 surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask_slice_tile_max);
1430 surf->color_initialized = true;
1434 struct r600_surface *surf)
1438 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1443 level = surf->base.u.tex.level;
1444 format = r600_translate_dbformat(surf->base.format);
1447 offset = r600_resource_va(screen, surf->base.texture);
1476 surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
1484 surf->db_depth_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1486 surf->db_depth_base = offset;
1487 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1488 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1489 surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1490 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1497 stencil_offset += r600_resource_va(screen, surf->base.texture);
1512 surf->db_stencil_base = stencil_offset;
1513 surf->db_stencil_info = 1 | S_028044_TILE_SPLIT(stile_split);
1515 surf->db_stencil_base = offset;
1516 surf->db_stencil_info = 1;
1519 surf->depth_initialized = true;
1697 struct r600_surface *surf;
1720 surf = (struct r600_surface*)state->cbufs[i];
1721 res = (struct r600_resource*)surf->base.texture;
1726 if (!surf->color_initialized) {
1727 evergreen_init_color_surface(rctx, surf);
1730 if (!surf->export_16bpc) {
1735 surf->cb_color_base, res, RADEON_USAGE_READWRITE);
1737 surf->cb_color_dim);
1739 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1741 surf->cb_color_pitch);
1743 surf->cb_color_slice);
1745 surf->cb_color_view);
1747 surf->cb_color_attrib, res, RADEON_USAGE_READWRITE);
1749 surf->cb_color_cmask, res, RADEON_USAGE_READWRITE);
1751 surf->cb_color_cmask_slice);
1753 surf->cb_color_fmask, res, RADEON_USAGE_READWRITE);
1755 surf->cb_color_fmask_slice);
1766 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1776 surf = (struct r600_surface*)state->cbufs[0];
1777 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1778 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1781 if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
1782 rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
1789 surf = (struct r600_surface*)state->zsbuf;
1790 res = (struct r600_resource*)surf->base.texture;
1794 if (!surf->depth_initialized) {
1795 evergreen_init_depth_surface(rctx, surf);
1798 r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE, surf->db_depth_base,
1800 r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE, surf->db_depth_base,
1802 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, surf->db_depth_view);
1804 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE, surf->db_stencil_base,
1806 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE, surf->db_stencil_base,
1808 r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO, surf->db_stencil_info,
1811 r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, surf->db_depth_info,
1813 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE, surf->db_depth_size);
1814 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE, surf->db_depth_slice);
