Lines Matching full:rstate
700 struct r600_pipe_state *rstate;
706 rstate = &blend->rstate;
708 rstate->id = R600_PIPE_STATE_BLEND;
774 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc);
776 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
779 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK,
787 return rstate;
803 struct r600_pipe_state *rstate;
814 rstate = &dsa->rstate;
816 rstate->id = R600_PIPE_STATE_DSA;
849 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
850 return rstate;
858 struct r600_pipe_state *rstate;
874 rstate = &rs->rstate;
893 rstate->id = R600_PIPE_STATE_RASTERIZER;
905 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
909 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
920 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
925 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
943 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
945 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
949 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
950 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
961 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
962 return rstate;
1134 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1137 if (rstate == NULL)
1141 rstate->id = R600_PIPE_STATE_CLIP;
1143 r600_pipe_state_add_reg(rstate,
1146 r600_pipe_state_add_reg(rstate,
1149 r600_pipe_state_add_reg(rstate,
1152 r600_pipe_state_add_reg(rstate,
1158 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1159 r600_context_pipe_state_set(rctx, rstate);
1177 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1180 if (rstate == NULL)
1183 rstate->id = R600_PIPE_STATE_SCISSOR;
1186 r600_pipe_state_add_reg(rstate,
1188 r600_pipe_state_add_reg(rstate,
1192 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1193 r600_context_pipe_state_set(rctx, rstate);
1215 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1217 if (rstate == NULL)
1221 rstate->id = R600_PIPE_STATE_VIEWPORT;
1222 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1223 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1224 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1225 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1226 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1227 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1230 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1231 r600_context_pipe_state_set(rctx, rstate);
1520 static uint32_t r600_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1545 r600_pipe_state_add_reg(rstate, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1548 r600_pipe_state_add_reg(rstate, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1551 r600_pipe_state_add_reg(rstate, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, sample_locs_8x[0]);
1552 r600_pipe_state_add_reg(rstate
1559 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0);
1560 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, 0);
1563 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_2x[0]);
1564 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_2x[1]);
1567 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_4x[0]);
1568 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_4x[1]);
1571 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_8x[0]);
1572 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_8x[1]);
1584 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1595 if (rstate == NULL)
1601 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1632 r600_pipe_state_add_reg_bo(rstate, R_028040_CB_COLOR0_BASE + i * 4,
1634 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + i * 4,
1636 r600_pipe_state_add_reg(rstate, R_028060_CB_COLOR0_SIZE + i * 4,
1638 r600_pipe_state_add_reg(rstate, R_028080_CB_COLOR0_VIEW + i * 4,
1640 r600_pipe_state_add_reg_bo(rstate, R_0280E0_CB_COLOR0_FRAG + i * 4,
1643 r600_pipe_state_add_reg_bo(rstate, R_0280C0_CB_COLOR0_TILE + i * 4,
1646 r600_pipe_state_add_reg(rstate, R_028100_CB_COLOR0_MASK + i * 4,
1655 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + 1 * 4,
1660 r600_pipe_state_add_reg(rstate, R_0280A0_CB_COLOR0_INFO + i * 4, 0);
1684 r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE, surf->db_depth_base,
1686 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, surf->db_depth_size);
1687 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, surf->db_depth_view);
1688 r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO, surf->db_depth_info,
1690 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1697 r600_pipe_state_add_reg(rstate,
1699 r600_pipe_state_add_reg(rstate,
1704 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL, 1);
1709 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1721 max_dist = r600_set_ms_pos(ctx, rstate, nr_samples);
1726 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL,
1729 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1733 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1734 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 0);
1738 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1739 r600_context_pipe_state_set(rctx, rstate);
2100 struct r600_pipe_state rstate;
2130 rstate.nregs = 0;
2131 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
2133 r600_context_pipe_state_set(rctx, &rstate);
2464 struct r600_pipe_state *rstate = &shader->rstate;
2472 rstate->nregs = 0;
2503 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2557 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2558 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2559 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2560 r600_pipe_state_add_reg_bo(rstate,
2563 r600_pipe_state_add_reg(rstate,
2568 r600_pipe_state_add_reg(rstate,
2583 struct r600_pipe_state *rstate = &shader->rstate;
2589 rstate->nregs = 0;
2600 r600_pipe_state_add_reg(rstate,
2612 r600_pipe_state_add_reg(rstate,
2615 r600_pipe_state_add_reg(rstate,
2619 r600_pipe_state_add_reg_bo(rstate,
2633 struct r600_pipe_state *rstate;
2636 rstate = &ve->rstate;
2637 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2638 rstate->nregs = 0;
2639 r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS,
2647 struct r600_pipe_state *rstate;
2662 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2663 return rstate;
2669 struct r600_pipe_state *rstate;
2674 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2675 return rstate;
2681 struct r600_pipe_state *rstate;
2686 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2687 return rstate;
2722 struct r600_pipe_state rstate;
2725 rstate.nregs = 0;
2726 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2727 r600_context_pipe_state_set(rctx, &rstate);
