Lines Matching defs:Rm
2129 int rm = instr->RmValue();
2132 int32_t rm_val = get_register(rm);
2138 // Format(instr, "mul'cond's 'rn, 'rm, 'rs");
2150 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
2153 // Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
2158 // Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
2174 // Format(instr, "'um'al'cond's 'rd, 'rn, 'rs, 'rm");
2209 int rm = instr->RmValue();
2210 int32_t rm_val = get_register(rm);
2213 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm");
2221 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
2229 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w");
2238 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w");
2339 int rm = instr->RmValue();
2340 DCHECK_NE(pc, rm); // UNPREDICTABLE
2343 SetSpecialRegister(sreg_and_mask, get_register(rm));
2352 int rm = instr->RmValue();
2355 set_pc(get_register(rm));
2359 set_pc(get_register(rm));
2373 int rm = instr->RmValue();
2377 uint32_t bits = get_register(rm);
2986 int rm = instr->RmValue();
2987 int32_t rm_val = get_register(rm);
2992 // Format(instr, "smmul'cond 'rn, 'rm, 'rs");
2996 // Format(instr, "smmla'cond 'rn, 'rm, 'rs, 'rd");
3008 // (s/u)div (in V8 notation matching ARM ISA format) rn = rm/rs
3009 // Format(instr, "'(s/u)div'cond'b 'rn, 'rm, 'rs);
3010 int rm = instr->RmValue();
3011 int32_t rm_val = get_register(rm);
3551 DCHECK((mode == RN) || (mode == RM) || (mode == RZ));
3570 case RM:
3630 DCHECK((mode == RM) || (mode == RZ) || (mode == RN));
3664 case RM:
3873 int Rm = instr->VmValue();
3902 if (Rm != 15) {
3903 if (Rm == 13) {
3906 Rm));
3914 int Rm = instr->VmValue();
3943 if (Rm != 15) {
3944 if (Rm == 13) {
3947 set_register(Rn, get_register(Rn) + get_register(Rm));
