Lines Matching refs:X10
70 AA0A014A (orr x10,x10,x10) X3 = client_request ( X4 )
230 #define X10 BITS2(1,0)
1203 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
6200 case 0x10: case 0x12: case 0x14: case 0x16:
7064 imm64 <<= 8; imm64 |= (imm8 & 0x10) ? 0xFF : 0x00;
7359 IRTemp x10 = src;
7362 assign(x11, binop(Iop_InterleaveHI64x2, mkexpr(x10), mkexpr(x10)));
7363 assign(x00, binop(Iop_InterleaveLO64x2, mkexpr(x10), mkexpr(x10)));
7520 case X10:
7569 case X10: amt = 32; break;
7705 case X10:
7918 vassert(size == X01 || size == X10); /* s or h only */
8450 if (size == X11 || (size == X10 && bitQ == 0)) return False;
8494 if (size == X10 && bitQ == 0) return False; // 2s case not allowed
8542 if ((size == X00 || size == X10)
9340 vassert(size >= X00 && size <= X10);
9394 vassert(size == X10 || size == X11);
9432 vassert(size == X10 || size == X11);
9741 if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,0,1,0)) {
9782 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10,
9789 if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,1,0,0)) {
9796 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10,
9815 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10,
9831 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10,
9961 if (size >= X10) {
9995 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10,
10123 if (size >= X10 && opcode == BITS5(1,1,1,0,1)) {
10132 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10,
10139 if (bitU == 0 && size >= X10 && opcode == BITS5(1,1,1,1,1)) {
10185 if (bitU == 0 && size >= X10
10220 if (size >= X10 && opcode == BITS4(1,0,0,1)) {
10271 case X10:
10314 case X10:
10749 vassert(size == X10 || size == X11);
10795 vassert(size == X10 || size == X11);
11577 IROp opMXX = (isMIN ? mkVecMINF : mkVecMAXF)(isD ? X11 : X10);
11633 if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,0,1,0)) {
11688 if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,1,0,0)) {
11839 if (bitU == 0 && size <= X10 && opcode == BITS5(0,0,0,0,0)) {
12075 if (size >= X10) {
12116 if (size >= X10 && opcode == BITS5(0,1,1,1,1)) {
12121 IROp op = isFNEG ? (size == X10 ? Iop_Neg32Fx4 : Iop_Neg64Fx2)
12122 : (size == X10 ? Iop_Abs32Fx4 : Iop_Abs64Fx2);
12399 if (size == X10 && opcode == BITS5(1,1,1,0,0)) {
12452 if (size >= X10 && opcode == BITS5(1,1,1,0,1)) {
12469 if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,1,1,1)) {
12516 if (bitU == 0 && size >= X10
12551 if (size >= X10 && opcode == BITS4(1,0,0,1)) {
12594 case X10:
12653 case X10:
12704 case X10:
12749 case X10:
13889 /* orr x10,x10,x10 */) {
