Lines Matching refs:am
213 ARM64AMode* am = LibVEX_Alloc_inline(sizeof(ARM64AMode));
214 am->tag = ARM64am_RI9;
215 am->ARM64am.RI9.reg = reg;
216 am->ARM64am.RI9.simm9 = simm9;
218 return am;
222 ARM64AMode* am = LibVEX_Alloc_inline(sizeof(ARM64AMode));
223 am->tag = ARM64am_RI12;
224 am->ARM64am.RI12.reg = reg;
225 am->ARM64am.RI12.uimm12 = uimm12;
226 am->ARM64am.RI12.szB = szB;
232 return am;
236 ARM64AMode* am = LibVEX_Alloc_inline(sizeof(ARM64AMode));
237 am->tag = ARM64am_RR;
238 am->ARM64am.RR.base = base;
239 am->ARM64am.RR.index = index;
240 return am;
243 static void ppARM64AMode ( ARM64AMode* am ) {
244 switch (am->tag) {
246 vex_printf("%d(", am->ARM64am.RI9.simm9);
247 ppHRegARM64(am->ARM64am.RI9.reg);
251 vex_printf("%u(", (UInt)am->ARM64am.RI12.szB
252 * (UInt)am->ARM64am.RI12.uimm12);
253 ppHRegARM64(am->ARM64am.RI12.reg);
258 ppHRegARM64(am->ARM64am.RR.base);
260 ppHRegARM64(am->ARM64am.RR.index);
268 static void addRegUsage_ARM64AMode ( HRegUsage* u, ARM64AMode* am ) {
269 switch (am->tag) {
271 addHRegUse(u, HRmRead, am->ARM64am.RI9.reg);
274 addHRegUse(u, HRmRead, am->ARM64am.RI12.reg);
277 addHRegUse(u, HRmRead, am->ARM64am.RR.base);
278 addHRegUse(u, HRmRead, am->ARM64am.RR.index);
285 static void mapRegs_ARM64AMode ( HRegRemap* m, ARM64AMode* am ) {
286 switch (am->tag) {
288 am->ARM64am.RI9.reg = lookupHRegRemap(m, am->ARM64am.RI9.reg);
291 am->ARM64am.RI12.reg = lookupHRegRemap(m, am->ARM64am.RI12.reg);
294 am->ARM64am.RR.base = lookupHRegRemap(m, am->ARM64am.RR.base);
295 am->ARM64am.RR.index = lookupHRegRemap(m, am->ARM64am.RR.index);
3049 Bool isLoad, UInt wD, ARM64AMode* am )
3052 if (am->tag == ARM64am_RI9) {
3056 Int simm9 = am->ARM64am.RI9.simm9;
3060 iregEnc(am->ARM64am.RI9.reg), wD);
3064 if (am->tag == ARM64am_RI12) {
3068 UInt uimm12 = am->ARM64am.RI12.uimm12;
3069 UInt scale = am->ARM64am.RI12.szB;
3071 UInt xN = iregEnc(am->ARM64am.RI12.reg);
3078 if (am->tag == ARM64am_RR) {
3082 UInt xN = iregEnc(am->ARM64am.RR.base);
3083 UInt xM = iregEnc(am->ARM64am.RR.index);
3098 Bool isLoad, UInt wD, ARM64AMode* am )
3101 if (am->tag == ARM64am_RI9) {
3105 Int simm9 = am->ARM64am.RI9.simm9;
3109 iregEnc(am->ARM64am.RI9.reg), wD);
3113 if (am->tag == ARM64am_RI12) {
3117 UInt uimm12 = am->ARM64am.RI12.uimm12;
3118 UInt scale = am->ARM64am.RI12.szB;
3120 UInt xN = iregEnc(am->ARM64am.RI12.reg);
3127 if (am->tag == ARM64am_RR) {
3131 UInt xN = iregEnc(am->ARM64am.RR.base);
3132 UInt xM = iregEnc(am->ARM64am.RR.index);
3147 Bool isLoad, UInt wD, ARM64AMode* am )
3150 if (am->tag == ARM64am_RI9) {
3154 Int simm9 = am->ARM64am.RI9.simm9;
3158 iregEnc(am->ARM64am.RI9.reg), wD);
3162 if (am->tag == ARM64am_RI12) {
3166 UInt uimm12 = am->ARM64am.RI12.uimm12;
3167 UInt scale = am->ARM64am.RI12.szB;
3169 UInt xN = iregEnc(am->ARM64am.RI12.reg);
3176 if (am->tag == ARM64am_RR) {
3180 UInt xN = iregEnc(am->ARM64am.RR.base);
3181 UInt xM = iregEnc(am->ARM64am.RR.index);
3196 Bool isLoad, UInt xD, ARM64AMode* am )
3200 if (am->tag == ARM64am_RI9) {
3204 Int simm9 = am->ARM64am.RI9.simm9;
3206 UInt xN = iregEnc(am->ARM64am.RI9.reg);
3213 if (am->tag == ARM64am_RI12) {
3217 UInt uimm12 = am->ARM64am.RI12.uimm12;
3218 UInt scale = am->ARM64am.RI12.szB;
3220 UInt xN = iregEnc(am->ARM64am.RI12.reg);
3227 if (am->tag == ARM64am_RR) {
3231 UInt xN = iregEnc(am->ARM64am.RR.base);
3232 UInt xM = iregEnc(am->ARM64am.RR.index);
