Lines Matching refs:Min
763 i->Min.LI.dst = dst;
764 i->Min.LI.imm = imm;
772 i->Min.Alu.op = op;
773 i->Min.Alu.dst = dst;
774 i->Min.Alu.srcL = srcL;
775 i->Min.Alu.srcR = srcR;
784 i->Min.Shft.op = op;
785 i->Min.Shft.sz32 = sz32;
786 i->Min.Shft.dst = dst;
787 i->Min.Shft.srcL = srcL;
788 i->Min.Shft.srcR = srcR;
796 i->Min.Unary.op = op;
797 i->Min.Unary.dst = dst;
798 i->Min.Unary.src = src;
807 i->Min.Cmp.syned = syned;
808 i->Min.Cmp.sz32 = sz32;
809 i->Min.Cmp.dst = dst;
810 i->Min.Cmp.srcL = srcL;
811 i->Min.Cmp.srcR = srcR;
812 i->Min.Cmp.cond = cond;
822 i->Min.Mul.syned = syned;
823 i->Min.Mul.widening = wid; /* widen=True else False */
824 i->Min.Mul.sz32 = sz32; /* True = 32 bits */
825 i->Min.Mul.dst = dst;
826 i->Min.Mul.srcL = srcL;
827 i->Min.Mul.srcR = srcR;
837 i->Min.Macc.op = Macc_SUB;
838 i->Min.Macc.syned = syned;
839 i->Min.Macc.srcL = srcL;
840 i->Min.Macc.srcR = srcR;
850 i->Min.Macc.op = Macc_ADD;
851 i->Min.Macc.syned = syned;
852 i->Min.Macc.srcL = srcL;
853 i->Min.Macc.srcR = srcR;
862 i->Min.Div.syned = syned;
863 i->Min.Div.sz32 = sz32; /* True = 32 bits */
864 i->Min.Div.srcL = srcL;
865 i->Min.Div.srcR = srcR;
875 i->Min.Call.cond = cond;
876 i->Min.Call.target = target;
877 i->Min.Call.argiregs = argiregs;
878 i->Min.Call.src = src;
879 i->Min.Call.rloc = rloc;
894 i->Min.Call.cond = cond;
895 i->Min.Call.target = target;
896 i->Min.Call.argiregs = argiregs;
897 i->Min.Call.rloc = rloc;
910 i->Min.XDirect.dstGA = dstGA;
911 i->Min.XDirect.amPC = amPC;
912 i->Min.XDirect.cond = cond;
913 i->Min.XDirect.toFastEP = toFastEP;
921 i->Min.XIndir.dstGA = dstGA;
922 i->Min.XIndir.amPC = amPC;
923 i->Min.XIndir.cond = cond;
931 i->Min.XAssisted.dstGA = dstGA;
932 i->Min.XAssisted.amPC = amPC;
933 i->Min.XAssisted.cond = cond;
934 i->Min.XAssisted.jk = jk;
942 i->Min.Load.sz = sz;
943 i->Min.Load.src = src;
944 i->Min.Load.dst = dst;
956 i->Min.Store.sz = sz;
957 i->Min.Store.src = src;
958 i->Min.Store.dst = dst;
970 i->Min.LoadL.sz = sz;
971 i->Min.LoadL.src = src;
972 i->Min.LoadL.dst = dst;
985 i->Min.Cas.sz = sz;
986 i->Min.Cas.old = old;
987 i->Min.Cas.addr = addr;
988 i->Min.Cas.expd = expd;
989 i->Min.Cas.data = data;
1001 i->Min.StoreC.sz = sz;
1002 i->Min.StoreC.src = src;
1003 i->Min.StoreC.dst = dst;
1015 i->Min.MtHL.src = src;
1023 i->Min.MtHL.src = src;
1031 i->Min.MfHL.dst = dst;
1039 i->Min.MfHL.dst = dst;
1048 i->Min.RdWrLR.wrLR = wrLR;
1049 i->Min.RdWrLR.gpr = gpr;
1057 i->Min.FpLdSt.isLoad = isLoad;
1058 i->Min.FpLdSt.sz = sz;
1059 i->Min.FpLdSt.reg = reg;
1060 i->Min.FpLdSt.addr = addr;
1069 i->Min.FpUnary.op = op;
1070 i->Min.FpUnary.dst = dst;
1071 i->Min.FpUnary.src = src;
1079 i->Min.FpBinary.op = op;
1080 i->Min.FpBinary.dst = dst;
1081 i->Min.FpBinary.srcL = srcL;
1082 i->Min.FpBinary.srcR = srcR;
1091 i->Min.FpTernary.op = op;
1092 i->Min.FpTernary.dst = dst;
1093 i->Min.FpTernary.src1 = src1;
1094 i->Min.FpTernary.src2 = src2;
1095 i->Min.FpTernary.src3 = src3;
1103 i->Min.FpConvert.op = op;
1104 i->Min.FpConvert.dst = dst;
1105 i->Min.FpConvert.src = src;
1114 i->Min.FpCompare.op = op;
1115 i->Min.FpCompare.dst = dst;
1116 i->Min.FpCompare.srcL = srcL;
1117 i->Min.FpCompare.srcR = srcR;
1125 i->Min.MtFCSR.src = src;
1133 i->Min.MfFCSR.dst = dst;
1141 i->Min.FpGpMove.op = op;
1142 i->Min.FpGpMove.dst = dst;
1143 i->Min.FpGpMove.src = src;
1152 i->Min.MoveCond.op = op;
1153 i->Min.MoveCond.dst = dst;
1154 i->Min.MoveCond.src = src;
1155 i->Min.MoveCond.cond = cond;
1163 i->Min.EvCheck.amCounter = amCounter;
1164 i->Min.EvCheck.amFailAddr = amFailAddr;
1186 ppLoadImm(i->Min.LI.dst, i->Min.LI.imm, mode64);
1189 HReg r_srcL = i->Min.Alu.srcL;
1190 MIPSRH *rh_srcR = i->Min.Alu.srcR;
1192 vex_printf("%s ", showMIPSAluOp(i->Min.Alu.op,
1194 ppHRegMIPS(i->Min.Alu.dst, mode64);
1202 HReg r_srcL = i->Min.Shft.srcL;
1203 MIPSRH *rh_srcR = i->Min.Shft.srcR;
1204 vex_printf("%s ", showMIPSShftOp(i->Min.Shft.op,
1206 i->Min.Shft.sz32));
1207 ppHRegMIPS(i->Min.Shft.dst, mode64);
1215 vex_printf("%s ", showMIPSUnaryOp(i->Min.Unary.op));
1216 ppHRegMIPS(i->Min.Unary.dst, mode64);
1218 ppHRegMIPS(i->Min.Unary.src, mode64);
1223 ppHRegMIPS(i->Min.Cmp.dst, mode64);
1224 vex_printf(" = %s ( ", showMIPSCondCode(i->Min.Cmp.cond));
1225 ppHRegMIPS(i->Min.Cmp.srcL, mode64);
1227 ppHRegMIPS(i->Min.Cmp.srcR, mode64);
1233 switch (i->Min.Mul.widening) {
1236 ppHRegMIPS(i->Min.Mul.dst, mode64);
1238 ppHRegMIPS(i->Min.Mul.srcL, mode64);
1240 ppHRegMIPS(i->Min.Mul.srcR, mode64);
1243 vex_printf("%s%s ", i->Min.Mul.sz32 ? "mult" : "dmult",
1244 i->Min.Mul.syned ? "" : "u");
1245 ppHRegMIPS(i->Min.Mul.dst, mode64);
1247 ppHRegMIPS(i->Min.Mul.srcL, mode64);
1249 ppHRegMIPS(i->Min.Mul.srcR, mode64);
1256 ppHRegMIPS(i->Min.MtHL.src, mode64);
1261 ppHRegMIPS(i->Min.MtHL.src, mode64);
1266 ppHRegMIPS(i->Min.MfHL.dst, mode64);
1271 ppHRegMIPS(i->Min.MfHL.dst, mode64);
1275 vex_printf("%s ", showMIPSMaccOp(i->Min.Macc.op, i->Min.Macc.syned));
1276 ppHRegMIPS(i->Min.Macc.srcL, mode64);
1278 ppHRegMIPS(i->Min.Macc.srcR, mode64);
1282 if (!i->Min.Div.sz32)
1285 vex_printf("%s ", i->Min.Div.syned ? "s" : "u");
1286 ppHRegMIPS(i->Min.Div.srcL, mode64);
1288 ppHRegMIPS(i->Min.Div.srcR, mode64);
1294 if (i->Min.Call.cond != MIPScc_AL) {
1295 vex_printf("if (%s) ", showMIPSCondCode(i->Min.Call.cond));
1301 ppLoadImm(hregMIPS_GPR25(mode64), i->Min.Call.target, mode64);
1305 if (i->Min.Call.argiregs & (1 << n)) {
1307 if ((i->Min.Call.argiregs >> n) > 1)
1320 showMIPSCondCode(i->Min.XDirect.cond));
1321 vex_printf("move $9, 0x%x,", (UInt)i->Min.XDirect.dstGA);
1323 ppMIPSAMode(i->Min.XDirect.amPC, mode64);
1325 i->Min.XDirect.toFastEP ? "fast" : "slow");
1330 showMIPSCondCode(i->Min.XIndir.cond));
1331 ppHRegMIPS(i->Min.XIndir.dstGA, mode64);
1333 ppMIPSAMode(i->Min.XIndir.amPC, mode64);
1339 showMIPSCondCode(i->Min.XAssisted.cond));
1341 ppHRegMIPS(i->Min.XAssisted.dstGA, mode64);
1343 ppMIPSAMode(i->Min.XAssisted.amPC, mode64);
1345 (Int)i->Min.XAssisted.jk);
1349 Bool idxd = toBool(i->Min.Load.src->tag == Mam_RR);
1350 UChar sz = i->Min.Load.sz;
1353 ppHRegMIPS(i->Min.Load.dst, mode64);
1355 ppMIPSAMode(i->Min.Load.src, mode64);
1359 UChar sz = i->Min.Store.sz;
1360 Bool idxd = toBool(i->Min.Store.dst->tag == Mam_RR);
1363 ppHRegMIPS(i->Min.Store.src, mode64);
1365 ppMIPSAMode(i->Min.Store.dst, mode64);
1370 ppHRegMIPS(i->Min.LoadL.dst, mode64);
1372 ppMIPSAMode(i->Min.LoadL.src, mode64);
1376 Bool sz8 = toBool(i->Min.Cas.sz == 8);
1390 ppHRegMIPS(i->Min.Cas.old , mode64);
1392 ppHRegMIPS(i->Min.Cas.addr , mode64);
1396 ppHRegMIPS(i->Min.Cas.old , mode64);
1398 ppHRegMIPS(i->Min.Cas.expd , mode64);
1404 ppHRegMIPS(i->Min.Cas.old , mode64);
1406 ppHRegMIPS(i->Min.Cas.old , mode64);
1410 ppHRegMIPS(i->Min.Cas.data , mode64);
1412 ppHRegMIPS(i->Min.Cas.addr , mode64);
1416 ppHRegMIPS(i->Min.Cas.old , mode64);
1418 ppHRegMIPS(i->Min.Cas.expd , mode64);
1420 ppHRegMIPS(i->Min.Cas.data , mode64);
1426 ppHRegMIPS(i->Min.StoreC.src, mode64);
1428 ppMIPSAMode(i->Min.StoreC.dst, mode64);
1432 vex_printf("%s ", i->Min.RdWrLR.wrLR ? "mtlr" : "mflr");
1433 ppHRegMIPS(i->Min.RdWrLR.gpr, mode64);
1437 vex_printf("%s ", showMIPSFpOp(i->Min.FpUnary.op));
1438 ppHRegMIPS(i->Min.FpUnary.dst, mode64);
1440 ppHRegMIPS(i->Min.FpUnary.src, mode64);
1443 vex_printf("%s", showMIPSFpOp(i->Min.FpBinary.op));
1444 ppHRegMIPS(i->Min.FpBinary.dst, mode64);
1446 ppHRegMIPS(i->Min.FpBinary.srcL, mode64);
1448 ppHRegMIPS(i->Min.FpBinary.srcR, mode64);
1451 vex_printf("%s", showMIPSFpOp(i->Min.FpTernary.op));
1452 ppHRegMIPS(i->Min.FpTernary.dst, mode64);
1454 ppHRegMIPS(i->Min.FpTernary.src1, mode64);
1456 ppHRegMIPS(i->Min.FpTernary.src2, mode64);
1458 ppHRegMIPS(i->Min.FpTernary.src3, mode64);
1461 vex_printf("%s", showMIPSFpOp(i->Min.FpConvert.op));
1462 ppHRegMIPS(i->Min.FpConvert.dst, mode64);
1464 ppHRegMIPS(i->Min.FpConvert.src, mode64);
1467 vex_printf("%s ", showMIPSFpOp(i->Min.FpCompare.op));
1468 ppHRegMIPS(i->Min.FpCompare.srcL, mode64);
1470 ppHRegMIPS(i->Min.FpCompare.srcR, mode64);
1473 vex_printf("%s ", showMIPSFpOp(i->Min.FpMulAcc.op));
1474 ppHRegMIPS(i->Min.FpMulAcc.dst, mode64);
1476 ppHRegMIPS(i->Min.FpMulAcc.srcML, mode64);
1478 ppHRegMIPS(i->Min.FpMulAcc.srcMR, mode64);
1480 ppHRegMIPS(i->Min.FpMulAcc.srcAcc, mode64);
1483 if (i->Min.FpLdSt.sz == 4) {
1484 if (i->Min.FpLdSt.isLoad) {
1486 ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
1488 ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
1491 ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
1493 ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
1495 } else if (i->Min.FpLdSt.sz == 8) {
1496 if (i->Min.FpLdSt.isLoad) {
1498 ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
1500 ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
1503 ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
1505 ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
1512 ppHRegMIPS(i->Min.MtFCSR.src, mode64);
1518 ppHRegMIPS(i->Min.MfFCSR.dst, mode64);
1523 vex_printf("%s ", showMIPSFpGpMoveOp(i->Min.FpGpMove.op));
1524 ppHRegMIPS(i->Min.FpGpMove.dst, mode64);
1526 ppHRegMIPS(i->Min.FpGpMove.src, mode64);
1530 vex_printf("%s", showMIPSMoveCondOp(i->Min.MoveCond.op));
1531 ppHRegMIPS(i->Min.MoveCond.dst, mode64);
1533 ppHRegMIPS(i->Min.MoveCond.src, mode64);
1535 ppHRegMIPS(i->Min.MoveCond.cond, mode64);
1540 ppMIPSAMode(i->Min.EvCheck.amCounter, mode64);
1543 ppMIPSAMode(i->Min.EvCheck.amCounter, mode64);
1545 ppMIPSAMode(i->Min.EvCheck.amFailAddr, mode64);
1577 addHRegUse(u, HRmWrite, i->Min.LI.dst);
1580 addHRegUse(u, HRmRead, i->Min.Alu.srcL);
1581 addRegUsage_MIPSRH(u, i->Min.Alu.srcR);
1582 addHRegUse(u, HRmWrite, i->Min.Alu.dst);
1585 addHRegUse(u, HRmRead, i->Min.Shft.srcL);
1586 addRegUsage_MIPSRH(u, i->Min.Shft.srcR);
1587 addHRegUse(u, HRmWrite, i->Min.Shft.dst);
1590 addHRegUse(u, HRmRead, i->Min.Cmp.srcL);
1591 addHRegUse(u, HRmRead, i->Min.Cmp.srcR);
1592 addHRegUse(u, HRmWrite, i->Min.Cmp.dst);
1595 addHRegUse(u, HRmRead, i->Min.Unary.src);
1596 addHRegUse(u, HRmWrite, i->Min.Unary.dst);
1599 addHRegUse(u, HRmWrite, i->Min.Mul.dst);
1600 addHRegUse(u, HRmRead, i->Min.Mul.srcL);
1601 addHRegUse(u, HRmRead, i->Min.Mul.srcR);
1607 addHRegUse(u, HRmRead, i->Min.MtHL.src);
1613 addHRegUse(u, HRmWrite, i->Min.MfHL.dst);
1616 addHRegUse(u, HRmRead, i->Min.MtFCSR.src);
1619 addHRegUse(u, HRmWrite, i->Min.MfFCSR.dst);
1624 addHRegUse(u, HRmRead, i->Min.Macc.srcL);
1625 addHRegUse(u, HRmRead, i->Min.Macc.srcR);
1630 addHRegUse(u, HRmRead, i->Min.Div.srcL);
1631 addHRegUse(u, HRmRead, i->Min.Div.srcR);
1637 if (i->Min.Call.cond != MIPScc_AL)
1638 addHRegUse(u, HRmRead, i->Min.Call.src);
1665 argir = i->Min.Call.argiregs;
1687 addRegUsage_MIPSAMode(u, i->Min.XDirect.amPC);
1690 addHRegUse(u, HRmRead, i->Min.XIndir.dstGA);
1691 addRegUsage_MIPSAMode(u, i->Min.XIndir.amPC);
1694 addHRegUse(u, HRmRead, i->Min.XAssisted.dstGA);
1695 addRegUsage_MIPSAMode(u, i->Min.XAssisted.amPC);
1698 addRegUsage_MIPSAMode(u, i->Min.Load.src);
1699 addHRegUse(u, HRmWrite, i->Min.Load.dst);
1702 addHRegUse(u, HRmRead, i->Min.Store.src);
1703 addRegUsage_MIPSAMode(u, i->Min.Store.dst);
1706 addRegUsage_MIPSAMode(u, i->Min.LoadL.src);
1707 addHRegUse(u, HRmWrite, i->Min.LoadL.dst);
1710 addHRegUse(u, HRmWrite, i->Min.Cas.old);
1711 addHRegUse(u, HRmRead, i->Min.Cas.addr);
1712 addHRegUse(u, HRmRead, i->Min.Cas.expd);
1713 addHRegUse(u, HRmModify, i->Min.Cas.data);
1716 addHRegUse(u, HRmWrite, i->Min.StoreC.src);
1717 addHRegUse(u, HRmRead, i->Min.StoreC.src);
1718 addRegUsage_MIPSAMode(u, i->Min.StoreC.dst);
1721 addHRegUse(u, (i->Min.RdWrLR.wrLR ? HRmRead : HRmWrite),
1722 i->Min.RdWrLR.gpr);
1725 if (i->Min.FpLdSt.sz == 4) {
1726 addHRegUse(u, (i->Min.FpLdSt.isLoad ? HRmWrite : HRmRead),
1727 i->Min.FpLdSt.reg);
1728 addRegUsage_MIPSAMode(u, i->Min.FpLdSt.addr);
1730 } else if (i->Min.FpLdSt.sz == 8) {
1731 addHRegUse(u, (i->Min.FpLdSt.isLoad ? HRmWrite : HRmRead),
1732 i->Min.FpLdSt.reg);
1733 addRegUsage_MIPSAMode(u, i->Min.FpLdSt.addr);
1738 addHRegUse(u, HRmWrite, i->Min.FpUnary.dst);
1739 addHRegUse(u, HRmRead, i->Min.FpUnary.src);
1742 addHRegUse(u, HRmWrite, i->Min.FpBinary.dst);
1743 addHRegUse(u, HRmRead, i->Min.FpBinary.srcL);
1744 addHRegUse(u, HRmRead, i->Min.FpBinary.srcR);
1747 addHRegUse(u, HRmWrite, i->Min.FpTernary.dst);
1748 addHRegUse(u, HRmRead, i->Min.FpTernary.src1);
1749 addHRegUse(u, HRmRead, i->Min.FpTernary.src2);
1750 addHRegUse(u, HRmRead, i->Min.FpTernary.src3);
1753 addHRegUse(u, HRmWrite, i->Min.FpConvert.dst);
1754 addHRegUse(u, HRmRead, i->Min.FpConvert.src);
1757 addHRegUse(u, HRmWrite, i->Min.FpCompare.dst);
1758 addHRegUse(u, HRmRead, i->Min.FpCompare.srcL);
1759 addHRegUse(u, HRmRead, i->Min.FpCompare.srcR);
1762 addHRegUse(u, HRmWrite, i->Min.FpGpMove.dst);
1763 addHRegUse(u, HRmRead, i->Min.FpGpMove.src);
1766 addHRegUse(u, HRmModify, i->Min.MoveCond.dst);
1767 addHRegUse(u, HRmRead, i->Min.MoveCond.src);
1768 addHRegUse(u, HRmRead, i->Min.MoveCond.cond);
1773 addRegUsage_MIPSAMode(u, i->Min.EvCheck.amCounter);
1774 addRegUsage_MIPSAMode(u, i->Min.EvCheck.amFailAddr);
1796 mapReg(m, &i->Min.LI.dst);
1799 mapReg(m, &i->Min.Alu.srcL);
1800 mapRegs_MIPSRH(m, i->Min.Alu.srcR);
1801 mapReg(m, &i->Min.Alu.dst);
1804 mapReg(m, &i->Min.Shft.srcL);
1805 mapRegs_MIPSRH(m, i->Min.Shft.srcR);
1806 mapReg(m, &i->Min.Shft.dst);
1809 mapReg(m, &i->Min.Cmp.srcL);
1810 mapReg(m, &i->Min.Cmp.srcR);
1811 mapReg(m, &i->Min.Cmp.dst);
1814 mapReg(m, &i->Min.Unary.src);
1815 mapReg(m, &i->Min.Unary.dst);
1818 mapReg(m, &i->Min.Mul.dst);
1819 mapReg(m, &i->Min.Mul.srcL);
1820 mapReg(m, &i->Min.Mul.srcR);
1824 mapReg(m, &i->Min.MtHL.src);
1828 mapReg(m, &i->Min.MfHL.dst);
1831 mapReg(m, &i->Min.Macc.srcL);
1832 mapReg(m, &i->Min.Macc.srcR);
1835 mapReg(m, &i->Min.Div.srcL);
1836 mapReg(m, &i->Min.Div.srcR);
1840 if (i->Min.Call.cond != MIPScc_AL)
1841 mapReg(m, &i->Min.Call.src);
1845 mapRegs_MIPSAMode(m, i->Min.XDirect.amPC);
1848 mapReg(m, &i->Min.XIndir.dstGA);
1849 mapRegs_MIPSAMode(m, i->Min.XIndir.amPC);
1852 mapReg(m, &i->Min.XAssisted.dstGA);
1853 mapRegs_MIPSAMode(m, i->Min.XAssisted.amPC);
1856 mapRegs_MIPSAMode(m, i->Min.Load.src);
1857 mapReg(m, &i->Min.Load.dst);
1860 mapReg(m, &i->Min.Store.src);
1861 mapRegs_MIPSAMode(m, i->Min.Store.dst);
1864 mapRegs_MIPSAMode(m, i->Min.LoadL.src);
1865 mapReg(m, &i->Min.LoadL.dst);
1868 mapReg(m, &i->Min.Cas.old);
1869 mapReg(m, &i->Min.Cas.addr);
1870 mapReg(m, &i->Min.Cas.expd);
1871 mapReg(m, &i->Min.Cas.data);
1874 mapReg(m, &i->Min.StoreC.src);
1875 mapRegs_MIPSAMode(m, i->Min.StoreC.dst);
1878 mapReg(m, &i->Min.RdWrLR.gpr);
1881 if (i->Min.FpLdSt.sz == 4) {
1882 mapReg(m, &i->Min.FpLdSt.reg);
1883 mapRegs_MIPSAMode(m, i->Min.FpLdSt.addr);
1885 } else if (i->Min.FpLdSt.sz == 8) {
1886 mapReg(m, &i->Min.FpLdSt.reg);
1887 mapRegs_MIPSAMode(m, i->Min.FpLdSt.addr);
1892 mapReg(m, &i->Min.FpUnary.dst);
1893 mapReg(m, &i->Min.FpUnary.src);
1896 mapReg(m, &i->Min.FpBinary.dst);
1897 mapReg(m, &i->Min.FpBinary.srcL);
1898 mapReg(m, &i->Min.FpBinary.srcR);
1901 mapReg(m, &i->Min.FpTernary.dst);
1902 mapReg(m, &i->Min.FpTernary.src1);
1903 mapReg(m, &i->Min.FpTernary.src2);
1904 mapReg(m, &i->Min.FpTernary.src3);
1907 mapReg(m, &i->Min.FpConvert.dst);
1908 mapReg(m, &i->Min.FpConvert.src);
1911 mapReg(m, &i->Min.FpCompare.dst);
1912 mapReg(m, &i->Min.FpCompare.srcL);
1913 mapReg(m, &i->Min.FpCompare.srcR);
1916 mapReg(m, &i->Min.MtFCSR.src);
1919 mapReg(m, &i->Min.MfFCSR.dst);
1922 mapReg(m, &i->Min.FpGpMove.dst);
1923 mapReg(m, &i->Min.FpGpMove.src);
1926 mapReg(m, &i->Min.MoveCond.dst);
1927 mapReg(m, &i->Min.MoveCond.src);
1928 mapReg(m, &i->Min.MoveCond.cond);
1933 mapRegs_MIPSAMode(m, i->Min.EvCheck.amCounter);
1934 mapRegs_MIPSAMode(m, i->Min.EvCheck.amFailAddr);
1956 if (i->Min.Alu.op != Malu_OR)
1958 if (i->Min.Alu.srcR->tag != Mrh_Reg)
1960 if (!sameHReg(i->Min.Alu.srcR->Mrh.Reg.reg, i->Min.Alu.srcL))
1962 *src = i->Min.Alu.srcL;
1963 *dst = i->Min.Alu.dst;
2523 p = mkLoadImm(p, iregNo(i->Min.LI.dst, mode64), i->Min.LI.imm, mode64);
2527 MIPSRH *srcR = i->Min.Alu.srcR;
2529 UInt r_dst = iregNo(i->Min.Alu.dst, mode64);
2530 UInt r_srcL = iregNo(i->Min.Alu.srcL, mode64);
2533 switch (i->Min.Alu.op) {
2635 MIPSRH *srcR = i->Min.Shft.srcR;
2636 Bool sz32 = i->Min.Shft.sz32;
2638 UInt r_dst = iregNo(i->Min.Shft.dst, mode64);
2639 UInt r_srcL = iregNo(i->Min.Shft.srcL, mode64);
2644 switch (i->Min.Shft.op) {
2732 UInt r_dst = iregNo(i->Min.Unary.dst, mode64);
2733 UInt r_src = iregNo(i->Min.Unary.src, mode64);
2735 switch (i->Min.Unary.op) {
2757 UInt r_srcL = iregNo(i->Min.Cmp.srcL, mode64);
2758 UInt r_srcR = iregNo(i->Min.Cmp.srcR, mode64);
2759 UInt r_dst = iregNo(i->Min.Cmp.dst, mode64);
2761 switch (i->Min.Cmp.cond) {
2801 Bool syned = i->Min.Mul.syned;
2802 Bool widening = i->Min.Mul.widening;
2803 Bool sz32 = i->Min.Mul.sz32;
2804 UInt r_srcL = iregNo(i->Min.Mul.srcL, mode64);
2805 UInt r_srcR = iregNo(i->Min.Mul.srcR, mode64);
2806 UInt r_dst = iregNo(i->Min.Mul.dst, mode64);
2834 Bool syned = i->Min.Macc.syned;
2835 UInt r_srcL = iregNo(i->Min.Macc.srcL, mode64);
2836 UInt r_srcR = iregNo(i->Min.Macc.srcR, mode64);
2839 switch (i->Min.Macc.op) {
2853 switch (i->Min.Macc.op) {
2873 Bool syned = i->Min.Div.syned;
2874 Bool sz32 = i->Min.Div.sz32;
2875 UInt r_srcL = iregNo(i->Min.Div.srcL, mode64);
2876 UInt r_srcR = iregNo(i->Min.Div.srcR, mode64);
2897 UInt r_src = iregNo(i->Min.MtHL.src, mode64);
2903 UInt r_src = iregNo(i->Min.MtHL.src, mode64);
2909 UInt r_dst = iregNo(i->Min.MfHL.dst, mode64);
2915 UInt r_dst = iregNo(i->Min.MfHL.dst, mode64);
2921 UInt r_src = iregNo(i->Min.MtFCSR.src, mode64);
2928 UInt r_dst = iregNo(i->Min.MfFCSR.dst, mode64);
2935 if (i->Min.Call.cond != MIPScc_AL
2936 && i->Min.Call.rloc.pri != RLPri_None) {
2946 MIPSCondCode cond = i->Min.Call.cond;
2965 p = mkLoadImm(p, r_dst, i->Min.Call.target, mode64);
2978 UInt r_src = iregNo(i->Min.Call.src, mode64);
3005 if (i->Min.XDirect.cond != MIPScc_AL) {
3006 vassert(i->Min.XDirect.cond != MIPScc_NV);
3014 p = mkLoadImm_EXACTLY2or6(p, /*r*/ 9, (ULong)i->Min.XDirect.dstGA,
3017 i->Min.XDirect.amPC, mode64);
3027 = i->Min.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP
3038 if (i->Min.XDirect.cond != MIPScc_AL) {
3067 if (i->Min.XIndir.cond != MIPScc_AL) {
3068 vassert(i->Min.XIndir.cond != MIPScc_NV);
3076 iregNo(i->Min.XIndir.dstGA, mode64),
3077 i->Min.XIndir.amPC, mode64);
3088 if (i->Min.XIndir.cond != MIPScc_AL) {
3108 if (i->Min.XAssisted.cond != MIPScc_AL) {
3109 vassert(i->Min.XAssisted.cond != MIPScc_NV);
3117 iregNo(i->Min.XIndir.dstGA, mode64),
3118 i->Min.XIndir.amPC, mode64);
3122 switch (i->Min.XAssisted.jk) {
3145 ppIRJumpKind(i->Min.XAssisted.jk);
3160 if (i->Min.XAssisted.cond != MIPScc_AL) {
3176 MIPSAMode *am_addr = i->Min.Load.src;
3178 UInt r_dst = iregNo(i->Min.Load.dst, mode64);
3179 UInt opc, sz = i->Min.Load.sz;
3205 UInt r_dst = iregNo(i->Min.Load.dst, mode64);
3206 UInt opc, sz = i->Min.Load.sz;
3233 MIPSAMode *am_addr = i->Min.Store.dst;
3235 UInt r_src = iregNo(i->Min.Store.src, mode64);
3236 UInt opc, sz = i->Min.Store.sz;
3262 UInt r_src = iregNo(i->Min.Store.src, mode64);
3263 UInt opc, sz = i->Min.Store.sz;
3289 MIPSAMode *am_addr = i->Min.LoadL.src;
3292 UInt r_dst = iregNo(i->Min.LoadL.dst, mode64);
3294 if (i->Min.LoadL.sz == 4)
3301 MIPSAMode *am_addr = i->Min.StoreC.dst;
3302 UInt r_src = iregNo(i->Min.StoreC.src, mode64);
3306 if (i->Min.StoreC.sz == 4)
3313 if (i->Min.Cas.sz != 8 && i->Min.Cas.sz != 4)
3315 UInt old = iregNo(i->Min.Cas.old, mode64);
3316 UInt addr = iregNo(i->Min.Cas.addr, mode64);
3317 UInt expd = iregNo(i->Min.Cas.expd, mode64);
3318 UInt data = iregNo(i->Min.Cas.data, mode64);
3319 Bool sz8 = toBool(i->Min.Cas.sz == 8);
3346 UInt reg = iregNo(i->Min.RdWrLR.gpr, mode64);
3347 Bool wrLR = i->Min.RdWrLR.wrLR;
3357 MIPSAMode *am_addr = i->Min.FpLdSt.addr;
3358 UChar sz = i->Min.FpLdSt.sz;
3361 UInt f_reg = fregNo(i->Min.FpLdSt.reg, mode64);
3362 if (i->Min.FpLdSt.isLoad) {
3374 UInt f_reg = dregNo(i->Min.FpLdSt.reg);
3375 if (i->Min.FpLdSt.isLoad) {
3393 switch (i->Min.FpUnary.op) {
3395 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3396 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3401 UInt fr_dst = dregNo(i->Min.FpUnary.dst);
3402 UInt fr_src = dregNo(i->Min.FpUnary.src);
3407 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3408 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3413 UInt fr_dst = dregNo(i->Min.FpUnary.dst);
3414 UInt fr_src = dregNo(i->Min.FpUnary.src);
3419 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3420 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3425 UInt fr_dst = dregNo(i->Min.FpUnary.dst);
3426 UInt fr_src = dregNo(i->Min.FpUnary.src);
3431 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3432 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3437 UInt fr_dst = dregNo(i->Min.FpUnary.dst);
3438 UInt fr_src = dregNo(i->Min.FpUnary.src);
3449 switch (i->Min.FpBinary.op) {
3451 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
3452 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
3453 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
3458 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
3459 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
3460 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
3465 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
3466 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
3467 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
3472 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
3473 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
3474 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
3479 UInt fr_dst = dregNo(i->Min.FpBinary.dst);
3480 UInt fr_srcL = dregNo(i->Min.FpBinary.srcL);
3481 UInt fr_srcR = dregNo(i->Min.FpBinary.srcR);
3486 UInt fr_dst = dregNo(i->Min.FpBinary.dst);
3487 UInt fr_srcL = dregNo(i->Min.FpBinary.srcL);
3488 UInt fr_srcR = dregNo(i->Min.FpBinary.srcR);
3493 UInt fr_dst = dregNo(i->Min.FpBinary.dst);
3494 UInt fr_srcL = dregNo(i->Min.FpBinary.srcL);
3495 UInt fr_srcR = dregNo(i->Min.FpBinary.srcR);
3500 UInt fr_dst = dregNo(i->Min.FpBinary.dst);
3501 UInt fr_srcL = dregNo(i->Min.FpBinary.srcL);
3502 UInt fr_srcR = dregNo(i->Min.FpBinary.srcR);
3513 switch (i->Min.FpTernary.op) {
3515 UInt fr_dst = fregNo(i->Min.FpTernary.dst, mode64);
3516 UInt fr_src1 = fregNo(i->Min.FpTernary.src1, mode64);
3517 UInt fr_src2 = fregNo(i->Min.FpTernary.src2, mode64);
3518 UInt fr_src3 = fregNo(i->Min.FpTernary.src3, mode64);
3523 UInt fr_dst = dregNo(i->Min.FpTernary.dst);
3524 UInt fr_src1 = dregNo(i->Min.FpTernary.src1);
3525 UInt fr_src2 = dregNo(i->Min.FpTernary.src2);
3526 UInt fr_src3 = dregNo(i->Min.FpTernary.src3);
3531 UInt fr_dst = fregNo(i->Min.FpTernary.dst, mode64);
3532 UInt fr_src1 = fregNo(i->Min.FpTernary.src1, mode64);
3533 UInt fr_src2 = fregNo(i->Min.FpTernary.src2, mode64);
3534 UInt fr_src3 = fregNo(i->Min.FpTernary.src3, mode64);
3539 UInt fr_dst = dregNo(i->Min.FpTernary.dst);
3540 UInt fr_src1 = dregNo(i->Min.FpTernary.src1);
3541 UInt fr_src2 = dregNo(i->Min.FpTernary.src2);
3542 UInt fr_src3 = dregNo(i->Min.FpTernary.src3);
3553 switch (i->Min.FpConvert.op) {
3556 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3557 fr_src = dregNo(i->Min.FpConvert.src);
3561 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3562 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3566 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3567 fr_src = dregNo(i->Min.FpConvert.src);
3571 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3572 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3576 fr_dst = dregNo(i->Min.FpConvert.dst);
3577 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3581 fr_dst = dregNo(i->Min.FpConvert.dst);
3582 fr_src = dregNo(i->Min.FpConvert.src);
3586 fr_dst = dregNo(i->Min.FpConvert.dst);
3587 fr_src = fregNo(i->Min
3591 fr_dst = dregNo(i->Min.FpConvert.dst);
3592 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3597 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3598 fr_src = dregNo(i->Min.FpConvert.src);
3600 fr_dst = dregNo(i->Min.FpConvert.dst);
3601 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3606 fr_dst = dregNo(i->Min.FpConvert.dst);
3607 fr_src = dregNo(i->Min.FpConvert.src);
3611 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3612 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3616 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3617 fr_src = dregNo(i->Min.FpConvert.src);
3621 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3622 fr_src = dregNo(i->Min.FpConvert.src);
3626 fr_dst = dregNo(i->Min.FpConvert.dst);
3627 fr_src = dregNo(i->Min.FpConvert.src);
3631 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3632 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3636 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3637 fr_src = dregNo(i->Min.FpConvert.src);
3641 fr_dst = dregNo(i->Min.FpConvert.dst);
3642 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3646 fr_dst = dregNo(i->Min.FpConvert.dst);
3647 fr_src = dregNo(i->Min.FpConvert.src);
3651 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3652 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3656 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3657 fr_src = dregNo(i->Min.FpConvert.src);
3661 fr_dst = dregNo(i->Min.FpConvert.dst);
3662 fr_src = dregNo(i->Min.FpConvert.src);
3666 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3667 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3671 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3672 fr_src = dregNo(i->Min.FpConvert.src);
3676 fr_dst = dregNo(i->Min.FpConvert.dst);
3677 fr_src = dregNo(i->Min.FpConvert.src);
3688 UInt r_dst = iregNo(i->Min.FpCompare.dst, mode64);
3689 UInt fr_srcL = dregNo(i->Min.FpCompare.srcL);
3690 UInt fr_srcR = dregNo(i->Min.FpCompare.srcR);
3693 switch (i->Min.FpConvert.op) {
3721 switch (i->Min.FpGpMove.op) {
3724 rt = iregNo(i->Min.FpGpMove.dst, mode64);
3725 fs = fregNo(i->Min.FpGpMove.src, mode64);
3731 rt = iregNo(i->Min.FpGpMove.dst, mode64);
3732 fs = fregNo(i->Min.FpGpMove.src, mode64);
3737 rt = iregNo(i->Min.FpGpMove.src, mode64);
3738 fs = fregNo(i->Min.FpGpMove.dst, mode64);
3744 rt = iregNo(i->Min.FpGpMove.src, mode64);
3745 fs = fregNo(i->Min.FpGpMove.dst, mode64);
3756 switch (i->Min.MoveCond.op) {
3759 d = fregNo(i->Min.MoveCond.dst, mode64);
3760 s = fregNo(i->Min.MoveCond.src, mode64);
3761 t = iregNo(i->Min.MoveCond.cond, mode64);
3766 d = dregNo(i->Min.MoveCond.dst);
3767 s = dregNo(i->Min.MoveCond.src);
3768 t = iregNo(i->Min.MoveCond.cond, mode64);
3773 d = iregNo(i->Min.MoveCond.dst, mode64);
3774 s = iregNo(i->Min.MoveCond.src, mode64);
3775 t = iregNo(i->Min.MoveCond.cond, mode64);
3800 i->Min.EvCheck.amCounter, mode64);
3805 i->Min.EvCheck.amCounter, mode64);
3810 i->Min.EvCheck.amFailAddr, mode64);
