Lines Matching defs:tst
120 do { tst->arch.vex.guest_LR = (zzval); \
121 VG_TRACK( post_reg_write, Vg_CoreSignal, tst->tid, \
127 do { tst->arch.vex.guest_GPR##zzn = (zzval); \
128 VG_TRACK( post_reg_write, Vg_CoreSignal, tst->tid, \
148 ThreadState* tst;
160 tst = VG_(get_ThreadState)(tid);
161 if (! ML_(sf_maybe_extend_stack)(tst, sp, sp_top_of_frame - sp, flags))
182 *(Addr *)sp = tst->arch.vex.guest_GPR1;
189 faultaddr = tst->arch.vex.guest_CIA;
198 frame->uc.uc_stack = tst->altstack;
199 frame->uc.uc_sigmask = tst->sig_mask;
204 = tst->arch.vex.guest_GPR##gpr
211 frame->uc.uc_mcontext.gp_regs[VKI_PT_NIP] = tst->arch.vex.guest_CIA;
217 frame->uc.uc_mcontext.gp_regs[VKI_PT_ORIG_R3] = tst->arch.vex.guest_GPR3;
218 frame->uc.uc_mcontext.gp_regs[VKI_PT_CTR] = tst->arch.vex.guest_CTR;
219 frame->uc.uc_mcontext.gp_regs[VKI_PT_LNK] = tst->arch.vex.guest_LR;
221 &tst->arch.vex);
223 &tst->arch.vex);
243 VG_TRACK(post_mem_write, Vg_CoreSignal, tst->tid,
251 SET_SIGNAL_LR(tst, (Addr)&VG_(ppc64_linux_SUBST_FOR_rt_sigreturn));
268 tst->arch.vex.guest_CIA = (Addr) ((ULong*)handler)[0];
271 tst->arch.vex.guest_CIA = (Addr) handler;
276 priv->vex_shadow1 = tst->arch.vex_shadow1;
277 priv->vex_shadow2 = tst->arch.vex_shadow2;
282 sp, tst->arch.vex.guest_CIA, (Int)tst->status);
293 ThreadState *tst;
302 tst = VG_(get_ThreadState)(tid);
305 sp = tst->arch.vex.guest_GPR1;
318 tst->sig_mask = frame->uc.uc_sigmask;
319 tst->tmp_sig_mask = tst->sig_mask;
323 # define DO(gpr) tst->arch.vex.guest_GPR##gpr \
331 tst->arch.vex.guest_CIA = frame->uc.uc_mcontext.gp_regs[VKI_PT_NIP];
334 &tst->arch.vex );
336 tst->arch.vex.guest_LR = frame->uc.uc_mcontext.gp_regs[VKI_PT_LNK];
337 tst->arch.vex.guest_CTR = frame->uc.uc_mcontext.gp_regs[VKI_PT_CTR];
339 &tst->arch.vex );
341 tst->arch.vex_shadow1 = priv->vex_shadow1;
342 tst->arch.vex_shadow2 = priv->vex_shadow2;
350 tid, has_siginfo, tst->arch.vex.guest_CIA);
