Lines Matching refs:LSL
139 ADD Counter, Temp, Counter, LSL #8 ;// [0 0 H W]
150 SUB pSrc, pSrc, srcStep, LSL #2
159 RSB ValCD0, ValEB0, ValCD0, LSL #2 ;// 4*(Off+C+D) - (Off+B+E)
161 LDR ValD, [pSrc, srcStep, LSL #1] ;// Load [d3 d2 d1 d0]
163 RSB ValCD1, ValEB1, ValCD1, LSL #2
167 LDR ValF, [pSrc, srcStep, LSL #2] ;// Load [f3 f2 f1 f0]
169 ADD ValCD0, ValCD0, ValCD0, LSL #2 ;// 5 * [4*(Off+C+D) - (Off+B+E)]
170 ADD ValCD1, ValCD1, ValCD1, LSL #2
173 RSB ValED1, ValCF1, ValED1, LSL #2
175 SUB ValA, pSrc, srcStep, LSL #1
177 RSB ValED0, ValCF0, ValED0, LSL #2 ;// 4*(Off+E+D) - (Off+C+F)
178 ADD ValED1, ValED1, ValED1, LSL #2
179 ADD ValED0, ValED0, ValED0, LSL #2 ;// 5 * [4*(Off+E+D) - (Off+C+F)]
186 LDR ValG, [pSrc, srcStep, LSL #2] ;// Load [g3 g2 g1 g0]
201 ADD pSrc, pSrc, srcStep, LSL #1
275 ORR Acc0, Acc0, Acc1, LSL #8
276 ORR Acc2, Acc2, Acc3, LSL #8
278 ORR Acc0, Acc0, Acc2, LSL #16
282 SUB pDst, pDst, dstStep, LSL #2
283 SUB pSrc, pSrc, srcStep, LSL #2
