Lines Matching refs:Rn
402 int s, int Rd, int Rn, uint32_t Op2)
418 mMips->AND(Rd, Rn, src);
420 mMips->ANDI(Rd, Rn, src);
427 mMips->ADDU(Rd, Rn, src);
429 mMips->ADDIU(Rd, Rn, src);
436 mMips->SUBU(Rd, Rn, src);
438 mMips->SUBIU(Rd, Rn, src);
445 mMips->DADDU(Rd, Rn, src);
447 mMips->DADDIU(Rd, Rn, src);
454 mMips->DSUBU(Rd, Rn, src);
456 mMips->DSUBIU(Rd, Rn, src);
462 mMips->XOR(Rd, Rn, src);
464 mMips->XORI(Rd, Rn, src);
470 mMips->OR(Rd, Rn, src);
472 mMips->ORI(Rd, Rn, src);
483 mMips->AND(Rd, Rn, R_at);
492 mMips->SUBU(Rd, src, Rn); // subu with the parameters reversed
566 cond.r1 = Rn;
605 int Rd, int Rm, int Rs, int Rn) {
611 mMips->ADDU(Rd, R_at, Rn);
746 void ArmToMips64Assembler::BX(int cc, int Rn)
760 void ArmToMips64Assembler::LDR(int cc, int Rd, int Rn, uint32_t offset)
771 if (Rn == ARMAssemblerInterface::SP) {
772 Rn = R_sp; // convert LDR via Arm SP to LW via Mips SP
774 mMips->LW(Rd, Rn, amode.value);
776 mMips->DADDIU(Rn, Rn, amode.value);
780 if (Rn == ARMAssemblerInterface::SP) {
781 Rn = R_sp; // convert STR thru Arm SP to STR thru Mips SP
783 mMips->LW(Rd, Rn, 0);
784 mMips->DADDIU(Rn, Rn, amode.value);
788 mMips->DADDU(R_at, Rn, amode.reg);
794 void ArmToMips64Assembler::LDRB(int cc, int Rd, int Rn, uint32_t offset)
805 mMips->LBU(Rd, Rn, amode.value);
807 mMips->DADDIU(Rn, Rn, amode.value);
811 mMips->LBU(Rd, Rn, 0);
812 mMips->DADDIU(Rn, Rn, amode.value);
816 mMips->DADDU(R_at, Rn, amode.reg);
823 void ArmToMips64Assembler::STR(int cc, int Rd, int Rn, uint32_t offset)
834 if (Rn == ARMAssemblerInterface::SP) {
835 Rn = R_sp; // convert STR thru Arm SP to SW thru Mips SP
840 mMips->DADDIU(Rn, Rn, amode.value);
841 mMips->SW(Rd, Rn, 0);
844 mMips->SW(Rd, Rn, amode.value);
848 mMips->SW(Rd, Rn, 0);
849 mMips->DADDIU(Rn, Rn, amode.value); // post index always writes back
853 mMips->DADDU(R_at, Rn, amode.reg);
859 void ArmToMips64Assembler::STRB(int cc, int Rd, int Rn, uint32_t offset)
870 mMips->SB(Rd, Rn, amode.value);
872 mMips->DADDIU(Rn, Rn, amode.value);
876 mMips->SB(Rd, Rn, 0);
877 mMips->DADDIU(Rn, Rn, amode.value);
881 mMips->DADDU(R_at, Rn, amode.reg);
887 void ArmToMips64Assembler::LDRH(int cc, int Rd, int Rn, uint32_t offset)
897 mMips->LHU(Rd, Rn, amode.value);
900 mMips->LHU(Rd, Rn, 0);
901 mMips->DADDIU(Rn, Rn, amode.value);
906 mMips->DADDU(R_at, Rn, amode.reg);
908 mMips->DSUBU(R_at, Rn, abs(amode.reg));
915 void ArmToMips64Assembler::LDRSB(int cc, int Rd, int Rn, uint32_t offset)
922 void ArmToMips64Assembler::LDRSH(int cc, int Rd, int Rn, uint32_t offset)
929 void ArmToMips64Assembler::STRH(int cc, int Rd, int Rn, uint32_t offset)
939 mMips->SH(Rd, Rn, amode.value);
942 mMips->SH(Rd, Rn, 0);
943 mMips->DADDIU(Rn, Rn, amode.value);
948 mMips->DADDU(R_at, Rn, amode.reg);
950 mMips->DSUBU(R_at, Rn, abs(amode.reg));
966 int Rn, int W, uint32_t reg_list)
971 // (uint32_t(U[dir])<<23) | (1<<20) | (W<<21) | (Rn<<16) | reg_list;
978 int Rn, int W, uint32_t reg_list)
983 // (uint32_t(U[dir])<<23) | (0<<20) | (W<<21) | (Rn<<16) | reg_list;
997 void ArmToMips64Assembler::SWP(int cc, int Rn, int Rd, int Rm) {
998 // *mPC++ = (cc<<28) | (2<<23) | (Rn<<16) | (Rd << 12) | 0x90 | Rm;
1004 void ArmToMips64Assembler::SWPB(int cc, int Rn, int Rd, int Rm) {
1005 // *mPC++ = (cc<<28) | (2<<23) | (1<<22) | (Rn<<16) | (Rd << 12) | 0x90 | Rm;
1025 void ArmToMips64Assembler::PLD(int Rn, uint32_t offset) {
1028 // *mPC++ = 0xF550F000 | (Rn<<16) | offset;
1040 void ArmToMips64Assembler::QADD(int cc, int Rd, int Rm, int Rn)
1042 // *mPC++ = (cc<<28) | 0x1000050 | (Rn<<16) | (Rd<<12) | Rm;
1048 void ArmToMips64Assembler::QDADD(int cc, int Rd, int Rm, int Rn)
1050 // *mPC++ = (cc<<28) | 0x1400050 | (Rn<<16) | (Rd<<12) | Rm;
1056 void ArmToMips64Assembler::QSUB(int cc, int Rd, int Rm, int Rn)
1058 // *mPC++ = (cc<<28) | 0x1200050 | (Rn<<16) | (Rd<<12) | Rm;
1064 void ArmToMips64Assembler::QDSUB(int cc, int Rd, int Rm, int Rn)
1066 // *mPC++ = (cc<<28) | 0x1600050 | (Rn<<16) | (Rd<<12) | Rm;
1120 // 16 x 16 signed multiply, accumulate: Rd = Rm{16} * Rs{16} + Rn
1122 int Rd, int Rm, int Rs, int Rn)
1148 mMips->ADDU(Rd, R_at, Rn);
1161 int Rd, int Rm, int Rs, int Rn)
1163 // *mPC++ = (cc<<28) | 0x1200080 | (Rd<<16) | (Rn<<12) | (Rs<<8) | (y<<4) | Rm;
1183 void ArmToMips64Assembler::UBFX(int cc, int Rd, int Rn, int lsb, int width)
1197 int s, int Rd, int Rn, uint32_t Op2)
1201 dataProcessing(opADD64, cc, s, Rd, Rn, Op2);
1205 int s, int Rd, int Rn, uint32_t Op2)
1209 dataProcessing(opSUB64, cc, s, Rd, Rn, Op2);
1212 void ArmToMips64Assembler::ADDR_LDR(int cc, int Rd, int Rn, uint32_t offset) {
1222 if (Rn == ARMAssemblerInterface::SP) {
1223 Rn = R_sp; // convert LDR via Arm SP to LW via Mips SP
1225 mMips->LD(Rd, Rn, amode.value);
1227 mMips->DADDIU(Rn, Rn, amode.value);
1231 if (Rn == ARMAssemblerInterface::SP) {
1232 Rn = R_sp; // convert STR thru Arm SP to STR thru Mips SP
1234 mMips->LD(Rd, Rn, 0);
1235 mMips->DADDIU(Rn, Rn, amode.value);
1239 mMips->DADDU(R_at, Rn, amode.reg);
1245 void ArmToMips64Assembler::ADDR_STR(int cc, int Rd, int Rn, uint32_t offset) {
1255 if (Rn == ARMAssemblerInterface::SP) {
1256 Rn = R_sp; // convert STR thru Arm SP to SW thru Mips SP
1261 mMips->DADDIU(Rn, Rn, amode.value);
1262 mMips->SD(Rd, Rn, 0);
1265 mMips->SD(Rd, Rn, amode.value);
1269 mMips->SD(Rd, Rn, 0);
1270 mMips->DADDIU(Rn, Rn, amode.value); // post index always writes back
1274 mMips->DADDU(R_at, Rn, amode.reg);
