Lines Matching refs:Rn
373 uint32_t Rn = R_t0, uint32_t Rm = R_t1, uint32_t Rs = R_t2)
387 regs[Rn] = test.RnValue;
412 case INSTR_ADD: a64asm->ADD(test.cond, test.setFlags, Rd,Rn,op2); break;
413 case INSTR_SUB: a64asm->SUB(test.cond, test.setFlags, Rd,Rn,op2); break;
414 case INSTR_RSB: a64asm->RSB(test.cond, test.setFlags, Rd,Rn,op2); break;
415 case INSTR_AND: a64asm->AND(test.cond, test.setFlags, Rd,Rn,op2); break;
416 case INSTR_ORR: a64asm->ORR(test.cond, test.setFlags, Rd,Rn,op2); break;
417 case INSTR_BIC: a64asm->BIC(test.cond, test.setFlags, Rd,Rn,op2); break;
419 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break;
420 case INSTR_CMP: a64asm->CMP(test.cond, Rn,op2); break;
429 case INSTR_SMLABB:a64asm->SMLABB(test.cond, Rd,Rm,Rs,Rn); break;
431 case INSTR_ADDR_ADD: a64asm->ADDR_ADD(test.cond, test.setFlags, Rd,Rn,op2); break;
432 case INSTR_ADDR_SUB: a64asm->ADDR_SUB(test.cond, test.setFlags, Rd,Rn,op2); break;
474 uint32_t Rd = R_v1, uint32_t Rn = R_t0,uint32_t Rm = R_t1)
488 regs[Rn] = (uint64_t)(&dataMem[test.RnValue]);
539 case INSTR_LDR: a64asm->LDR(test.cond, Rd,Rn,op2); break;
540 case INSTR_LDRB: a64asm->LDRB(test.cond, Rd,Rn,op2); break;
541 case INSTR_LDRH: a64asm->LDRH(test.cond, Rd,Rn,op2); break;
542 case INSTR_ADDR_LDR: a64asm->ADDR_LDR(test.cond, Rd,Rn,op2); break;
543 case INSTR_STR: a64asm->STR(test.cond, Rd,Rn,op2); break;
544 case INSTR_STRB: a64asm->STRB(test.cond, Rd,Rn,op2); break;
545 case INSTR_STRH: a64asm->STRH(test.cond, Rd,Rn,op2); break;
546 case INSTR_ADDR_STR: a64asm->ADDR_STR(test.cond, Rd,Rn,op2); break;
559 /* Check if all regs except Rd/Rn are same */
562 if(i == Rd || i == Rn || i == R_v0) continue;
579 else if((uint64_t)regs[Rn] != (uint64_t)(&dataMem[test.postRnValue]))
582 "Expected in Rn(0x%" PRIx64 "), Actual(0x%" PRIx64 ")\n",
583 test.id, test.postRnValue, regs[Rn] - (uint64_t)dataMem);
