Lines Matching refs:HW_H_SINT
564 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
1070 { "pcrel8a2", MEP_OPERAND_PCREL8A2, HW_H_SINT, 8, 7,
1074 { "pcrel12a2", MEP_OPERAND_PCREL12A2, HW_H_SINT, 4, 11,
1078 { "pcrel17a2", MEP_OPERAND_PCREL17A2, HW_H_SINT, 16, 16,
1082 { "pcrel24a2", MEP_OPERAND_PCREL24A2, HW_H_SINT, 5, 23,
1090 { "sdisp16", MEP_OPERAND_SDISP16, HW_H_SINT, 16, 16,
1094 { "simm16", MEP_OPERAND_SIMM16, HW_H_SINT, 16, 16,
1106 { "udisp2", MEP_OPERAND_UDISP2, HW_H_SINT, 6, 2,
1114 { "simm6", MEP_OPERAND_SIMM6, HW_H_SINT, 8, 6,
1118 { "simm8", MEP_OPERAND_SIMM8, HW_H_SINT, 8, 8,
1174 { "cdisp10", MEP_OPERAND_CDISP10, HW_H_SINT, 22, 10,
1178 { "cdisp10a2", MEP_OPERAND_CDISP10A2, HW_H_SINT, 22, 10,
1182 { "cdisp10a4", MEP_OPERAND_CDISP10A4, HW_H_SINT, 22, 10,
1186 { "cdisp10a8", MEP_OPERAND_CDISP10A8, HW_H_SINT, 22, 10,
1190 { "zero", MEP_OPERAND_ZERO, HW_H_SINT, 0, 0,
1198 { "cdisp12", MEP_OPERAND_CDISP12, HW_H_SINT, 20, 12,
1354 { "simm8p4", MEP_OPERAND_SIMM8P4, HW_H_SINT, 4, 8,
1398 { "simm8p0", MEP_OPERAND_SIMM8P0, HW_H_SINT, 0, 8,
1402 { "simm8p20", MEP_OPERAND_SIMM8P20, HW_H_SINT, 20, 8,
1442 { "simm16p0", MEP_OPERAND_SIMM16P0, HW_H_SINT, 0, 16,
