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Lines Matching refs:PTR

635   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
636 { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
637 { "h-ext", HW_H_EXT, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_ext_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
638 { "h-psw", HW_H_PSW, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_psw_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
639 { "h-grb", HW_H_GRB, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
640 { "h-cc", HW_H_CC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_conditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
641 { "h-ecc", HW_H_ECC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_extconditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
642 { "h-grb8", HW_H_GRB8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
643 { "h-r8", HW_H_R8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_r8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
644 { "h-regmem8", HW_H_REGMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regmem8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
645 { "h-regdiv8", HW_H_REGDIV8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regdiv8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
646 { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
647 { "h-r01", HW_H_R01, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name1, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
648 { "h-regbmem8", HW_H_REGBMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regbmem8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
649 { "h-memgr8", HW_H_MEMGR8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_memgr8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
741 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_NIL] } },
745 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
749 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
753 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R4] } },
757 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
761 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
765 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R0] } },
769 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
773 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
777 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
781 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
785 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM2] } },
789 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM3] } },
793 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
797 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM7] } },
801 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM8] } },
805 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
809 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
813 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
817 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
821 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
825 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGOFF8] } },
829 PTR) &xc16x_cgen_ifld_table[XC16X_F_REGHI8] } },
833 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
837 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
841 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
845 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEGNUM8] } },
849 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
853 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REL8] } },
857 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_RELHI8] } },
861 { 0, { (const PTR) 0 } },
865 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT1] } },
869 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT2] } },
873 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT4] } },
877 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT4] } },
881 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT2] } },
885 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT8] } },
889 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
893 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_ONEBIT] } },
897 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_1BIT] } },
901 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_CONDCODE] } },
905 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_ICONDCODE] } },
909 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_EXTCCODE] } },
913 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
917 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMGR8] } },
921 { 0, { (const PTR) 0 } },
925 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QBIT] } },
929 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QLOBIT] } },
933 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QHIBIT] } },
937 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MASK8] } },
941 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
945 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_PAGENUM] } },
949 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATA8] } },
953 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
957 { 0, { (const PTR) 0 } },
961 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
965 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
969 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
973 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
977 { 0, { (const PTR) 0 } },
981 { 0, { (const PTR) 0 } },
985 { 0, { (const PTR) 0 } },
989 { 0, { (const PTR) 0 } },
993 { 0, { (const PTR) 0 } },
997 { 0, { (const PTR) 0 } },
1001 { 0, { (const PTR) 0 } },