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Searched
defs:DefIdx
(Results
1 - 12
of
12
) sorted by null
/external/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.h
131
unsigned
DefIdx
;
149
return
DefIdx
-1;
/external/llvm/lib/CodeGen/
TargetSchedule.cpp
128
unsigned
DefIdx
= 0;
132
++
DefIdx
;
134
return
DefIdx
;
188
unsigned
DefIdx
= findDefIdx(DefMI, DefOperIdx);
189
if (
DefIdx
< SCDesc->NumWriteLatencyEntries) {
192
STI->getWriteLatencyEntry(SCDesc,
DefIdx
);
208
// If
DefIdx
does not exist in the model (e.g. implicit defs), then return
214
errs() << "
DefIdx
" <<
DefIdx
<< " exceeds machine model writes for "
228
for (unsigned
DefIdx
= 0, DefEnd = SCDesc.NumWriteLatencyEntries
[
all
...]
LiveRangeCalc.cpp
46
SlotIndex
DefIdx
=
50
LR.createDeadDef(
DefIdx
, Alloc);
179
unsigned
DefIdx
;
182
else if (MI->isRegTiedToDefOperand(OpNo, &
DefIdx
)) {
185
isEarlyClobber = MI->getOperand(
DefIdx
).isEarlyClobber();
RegAllocFast.cpp
743
unsigned
DefIdx
= 0;
744
if (!MI->isRegTiedToDefOperand(i, &
DefIdx
)) continue;
746
<<
DefIdx
<< ".\n");
[
all
...]
InlineSpiller.cpp
[
all
...]
MachineInstr.cpp
815
int
DefIdx
= MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
816
if (
DefIdx
!= -1)
817
tieOperands(
DefIdx
, OpNo);
[
all
...]
MachineVerifier.cpp
[
all
...]
RegisterCoalescer.cpp
661
int
DefIdx
= DefMI->findRegisterDefOperandIdx(IntA.reg);
662
assert(
DefIdx
!= -1);
664
if (!DefMI->isRegTiedToUseOperand(
DefIdx
, &UseOpIdx))
770
SlotIndex
DefIdx
= UseIdx.getRegSlot();
771
VNInfo *DVNI = IntB.getVNInfoAt(
DefIdx
);
774
DEBUG(dbgs() << "\t\tnoop: " <<
DefIdx
<< '\t' << *UseMI);
775
assert(DVNI->def ==
DefIdx
);
778
VNInfo *SubDVNI = S.getVNInfoAt(
DefIdx
);
[
all
...]
/external/llvm/lib/Target/Sparc/
SparcISelDAGToDAG.cpp
206
unsigned
DefIdx
= 0;
210
if (Changed && InlineAsm::isUseOperandTiedToDef(Flag,
DefIdx
))
211
IsTiedToChangedOp = OpChanged[
DefIdx
];
297
Flag = InlineAsm::getFlagWordForMatchingOp(Flag,
DefIdx
);
/external/llvm/lib/Target/PowerPC/
PPCVSXSwapRemoval.cpp
617
int
DefIdx
= SwapMap[DefMI];
618
(void)EC->unionSets(SwapVector[
DefIdx
].VSEId,
621
DEBUG(dbgs() << format("Unioning %d with %d\n", SwapVector[
DefIdx
].VSEId,
695
int
DefIdx
= SwapMap[DefMI];
697
if (!SwapVector[
DefIdx
].IsSwap || SwapVector[
DefIdx
].IsLoad ||
698
SwapVector[
DefIdx
].IsStore) {
704
DEBUG(dbgs() << " def " <<
DefIdx
<< ": ");
751
int
DefIdx
= SwapMap[DefMI];
752
SwapVector[
DefIdx
].WillRemove = 1
[
all
...]
/external/llvm/lib/CodeGen/MIRParser/
MIParser.cpp
887
unsigned
DefIdx
= Operands[I].TiedDefIdx.getValue();
888
if (
DefIdx
>= E)
891
Twine(
DefIdx
) + "'; instruction has only ") +
893
const auto &DefOperand = Operands[
DefIdx
].Operand;
898
Twine(
DefIdx
) + "'; the operand #" + Twine(
DefIdx
) +
902
if (TiedPair.first ==
DefIdx
)
904
Twine("the tied-def operand #") + Twine(
DefIdx
) +
907
TiedRegisterPairs.push_back(std::make_pair(
DefIdx
, I));
[
all
...]
/external/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp
[
all
...]
Completed in 264 milliseconds