HomeSort by relevance Sort by last modified time
    Searched defs:DstReg (Results 1 - 25 of 48) sorted by null

1 2

  /external/llvm/lib/Target/AArch64/
AArch64ExpandPseudoInsts.cpp 117 const unsigned DstReg = MI.getOperand(0).getReg();
121 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
122 .addReg(DstReg)
182 const unsigned DstReg = MI.getOperand(0).getReg();
198 .addReg(DstReg,
200 .addReg(DstReg)
223 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
224 .addReg(DstReg)
365 const unsigned DstReg = MI.getOperand(0).getReg();
372 .addReg(DstReg,
    [all...]
  /external/llvm/lib/CodeGen/
ExpandPostRAPseudos.cpp 87 unsigned DstReg = MI->getOperand(0).getReg();
93 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
95 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
113 if (DstReg != InsReg) {
125 // Implicitly define DstReg for subsequent uses.
128 CopyMI->addRegisterDefined(DstReg);
OptimizePHIs.cpp 92 unsigned DstReg = MI->getOperand(0).getReg();
105 if (SrcReg == DstReg)
135 unsigned DstReg = MI->getOperand(0).getReg();
136 assert(TargetRegisterInfo::isVirtualRegister(DstReg) &&
147 for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) {
RegisterCoalescer.h 33 unsigned DstReg;
35 /// The virtual register that will be coalesced into dstReg.
38 /// The sub-register index of the old DstReg in the new coalesced register.
50 /// True when DstReg and SrcReg are reversed from the original
54 /// The register class of the coalesced register, or NULL if DstReg
56 /// SrcReg and DstReg.
61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
75 /// Swap SrcReg and DstReg. Return false if swapping is impossible
76 /// because DstReg is a physical register, or SubIdx is set
    [all...]
MachineSink.cpp 163 unsigned DstReg = MI->getOperand(0).getReg();
165 !TargetRegisterInfo::isVirtualRegister(DstReg) ||
170 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
179 MRI->replaceRegWith(DstReg, SrcReg);
EarlyIfConversion.cpp 113 // Latencies from Cond+Branch, TReg, and FReg to DstReg.
463 unsigned DstReg = PI.PHI->getOperand(0).getReg();
464 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
482 unsigned DstReg = 0;
488 DstReg = PI.TReg;
491 DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst));
493 DstReg, Cond, PI.TReg, PI.FReg);
497 // Rewrite PHI operands TPred -> (DstReg, Head), remove FPred.
502 PI.PHI->getOperand(i-2).setReg(DstReg);
RegAllocPBQP.cpp 419 unsigned DstReg = CP.getDstReg();
426 if (!MF.getRegInfo().isAllocatable(DstReg))
435 while (PRegOpt < Allowed.size() && Allowed[PRegOpt] != DstReg)
444 PBQPRAGraph::NodeId N1Id = G.getMetadata().getNodeIdForVReg(DstReg);
  /external/llvm/lib/Target/Hexagon/
HexagonExpandPredSpillCode.cpp 287 // DstReg = LDriw_pred [R30], ofst.
288 int DstReg = MI->getOperand(0).getReg();
289 assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
310 DstReg).addReg(HEXAGON_RESERVED_REG_2);
319 DstReg).addReg(HEXAGON_RESERVED_REG_2);
325 DstReg).addReg(HEXAGON_RESERVED_REG_2);
HexagonPeephole.cpp 141 unsigned DstReg = Dst.getReg();
144 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
149 PeepholeMap[DstReg] = SrcReg;
163 unsigned DstReg = Dst.getReg();
165 PeepholeMap[DstReg] = SrcReg;
180 unsigned DstReg = Dst.getReg();
182 PeepholeDoubleRegsMap[DstReg] =
192 unsigned DstReg = Dst.getReg();
195 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
200 PeepholeMap[DstReg] = SrcReg
    [all...]
  /external/llvm/lib/Target/MSP430/
MSP430RegisterInfo.cpp 143 unsigned DstReg = MI.getOperand(0).getReg();
145 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
146 .addReg(DstReg).addImm(-Offset);
148 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
149 .addReg(DstReg).addImm(Offset);
  /external/mesa3d/src/gallium/drivers/radeon/
R600ExpandSpecialInstrs.cpp 96 unsigned DstReg = MI.getOperand(0).getReg();
120 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
124 Flags |= (Chan != TRI.getHWRegChan(DstReg) ? MO_FLAG_MASK : 0);
125 unsigned DstBase = TRI.getHWRegIndex(DstReg);
126 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
  /external/llvm/lib/Target/AMDGPU/
R600ExpandSpecialInstrs.cpp 126 unsigned DstReg;
129 DstReg = MI.getOperand(Chan).getReg();
131 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W;
134 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
155 unsigned DstReg;
158 DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y;
160 DstReg = MI.getOperand(Chan-2).getReg();
163 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
183 unsigned DstReg = MI.getOperand(0).getReg();
187 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg)
    [all...]
SIFixSGPRCopies.cpp 132 unsigned DstReg = Copy.getOperand(0).getReg();
144 TargetRegisterInfo::isVirtualRegister(DstReg) ?
145 MRI.getRegClass(DstReg) :
146 TRI.getPhysRegClass(DstReg);
182 unsigned DstReg = MI.getOperand(0).getReg();
183 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg)))
186 if (!MRI.hasOneUse(DstReg))
189 MachineInstr &CopyUse = *MRI.use_instr_begin(DstReg);
204 MRI.setRegClass(DstReg, DstRC);
SIShrinkInstructions.cpp 251 unsigned DstReg = MI.getOperand(0).getReg();
252 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
264 if (DstReg != AMDGPU::VCC)
R600OptimizeVectorRegisters.cpp 191 unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
197 DstReg)
211 SrcVec = DstReg;
  /external/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCDuplexInfo.cpp 181 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
192 DstReg = MCI.getOperand(0).getReg();
196 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {
210 DstReg = MCI.getOperand(0).getReg();
212 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
231 DstReg = MCI.getOperand(0).getReg();
233 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
241 DstReg = MCI.getOperand(0).getReg();
243 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
251 DstReg = MCI.getOperand(0).getReg()
    [all...]
HexagonMCCompound.cpp 84 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
100 DstReg = MI.getOperand(0).getReg();
103 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
114 DstReg = MI.getOperand(0).getReg();
116 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
126 DstReg = MI.getOperand(0).getReg();
128 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
136 DstReg = MI.getOperand(0).getReg()
    [all...]
  /external/mesa3d/src/mesa/main/
atifragshader.h 56 struct atifragshader_dst_register DstReg[2];
  /external/llvm/lib/Target/ARM/
MLxExpansionPass.cpp 275 unsigned DstReg = MI->getOperand(0).getReg();
301 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
Thumb2ITBlockPass.cpp 132 unsigned DstReg = MI->getOperand(0).getReg();
136 if (Uses.count(DstReg) || Defs.count(SrcReg))
  /external/llvm/lib/Target/Mips/
MipsOptimizePICCall.cpp 135 unsigned DstReg = getRegTy(SrcReg, MF) == MVT::i32 ? Mips::T9 : Mips::T9_64;
136 BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg)
138 I->getOperand(0).setReg(DstReg);
MipsSEInstrInfo.cpp 551 unsigned DstReg = I->getOperand(0).getReg();
552 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
553 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
568 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
577 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
580 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
583 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
589 unsigned DstReg = I->getOperand(0).getReg()
    [all...]
  /external/llvm/lib/Target/X86/
X86FixupLEAs.cpp 246 unsigned DstReg = LEA->getOperand(0).getReg();
248 return SrcReg == DstReg &&
  /external/mesa3d/src/gallium/drivers/r300/compiler/
radeon_program.h 79 struct rc_dst_register DstReg;
  /external/llvm/lib/Target/PowerPC/
PPCVSXSwapRemoval.cpp 152 // Insert a swap instruction from SrcReg to DstReg at the given
155 unsigned DstReg, unsigned SrcReg);
772 // then instead we should generate a copy from Reg to DstReg.
775 unsigned DstReg, unsigned SrcReg) {
777 TII->get(PPC::XXPERMDI), DstReg)
856 unsigned DstReg = MI->getOperand(0).getReg();
857 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
884 TII->get(PPC::COPY), DstReg)
889 insertSwap(MI, InsertPoint, DstReg, NewVReg);
    [all...]

Completed in 2142 milliseconds

1 2