1 /* 2 * Copyright (C) 2016 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef _CMSIS_H_ 18 #define _CMSIS_H_ 19 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 #define __NVIC_PRIO_BITS 4 26 #define __FPU_PRESENT 1 27 28 29 30 typedef enum IRQn 31 { 32 /* ------------------- Cortex Processor Exceptions Numbers ------------------ */ 33 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 34 HardFault_IRQn = -13, /*!< 3 HardFault Interrupt */ 35 MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */ 36 BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */ 37 UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */ 38 SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */ 39 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */ 40 PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */ 41 SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */ 42 43 /* ---------------------- STM32F411 Specific Interrupt Numbers ----------------- */ 44 WWDG_IRQn = 0, 45 PVD_IRQn = 1, 46 TAMP_STAMP_IRQn = 2, 47 RTC_WKUP_IRQn = 3, 48 FLASH_IRQn = 4, 49 RCC_IRQn = 5, 50 EXTI0_IRQn = 6, 51 EXTI1_IRQn = 7, 52 EXTI2_IRQn = 8, 53 EXTI3_IRQn = 9, 54 EXTI4_IRQn = 10, 55 DMA1_Stream0_IRQn = 11, 56 DMA1_Stream1_IRQn = 12, 57 DMA1_Stream2_IRQn = 13, 58 DMA1_Stream3_IRQn = 14, 59 DMA1_Stream4_IRQn = 15, 60 DMA1_Stream5_IRQn = 16, 61 DMA1_Stream6_IRQn = 17, 62 ADC_IRQn = 18, 63 CAN1_TX_IRQn = 19, 64 CAN1_RX0_IRQn = 20, 65 CAN1_RX1_IRQn = 21, 66 CAN1_SCE_IRQn = 22, 67 EXTI9_5_IRQn = 23, 68 TIM1_BRK_TIM9_IRQn = 24, 69 TIM1_UP_TIM10_IRQn = 25, 70 TIM1_TRG_COM_TIM11_IRQn = 26, 71 TIM1_CC_IRQn = 27, 72 TIM2_IRQn = 28, 73 TIM3_IRQn = 29, 74 TIM4_IRQn = 30, 75 I2C1_EV_IRQn = 31, 76 I2C1_ER_IRQn = 32, 77 I2C2_EV_IRQn = 33, 78 I2C2_ER_IRQn = 34, 79 SPI1_IRQn = 35, 80 SPI2_IRQn = 36, 81 USART1_IRQn = 37, 82 USART2_IRQn = 38, 83 USART3_IRQn = 39, 84 EXTI15_10_IRQn = 40, 85 RTC_Alarm_IRQn = 41, 86 OTG_FS_WKUP_IRQn = 42, 87 TIM8_BRK_TIM12_IRQn = 43, 88 TIM8_UP_TIM13_IRQn = 44, 89 TIM8_TRG_COM_TIM14_IRQn = 45, 90 TIM8_CC_IRQn = 46, 91 DMA1_Stream7_IRQn = 47, 92 FSMC_IRQn = 48, 93 SDIO_IRQn = 49, 94 TIM5_IRQn = 50, 95 SPI3_IRQn = 51, 96 UART4_IRQn = 52, 97 UART5_IRQn = 53, 98 TIM6_DAC_IRQn = 54, 99 TIM7_IRQn = 55, 100 DMA2_Stream0_IRQn = 56, 101 DMA2_Stream1_IRQn = 57, 102 DMA2_Stream2_IRQn = 58, 103 DMA2_Stream3_IRQn = 59, 104 DMA2_Stream4_IRQn = 60, 105 ETH_IRQn = 61, 106 ETH_WKUP_IRQn = 62, 107 CAN2_TX_IRQn = 63, 108 CAN2_RX0_IRQn = 64, 109 CAN2_RX1_IRQn = 65, 110 CAN2_SCE_IRQn = 66, 111 OTG_FS_IRQn = 67, 112 DMA2_Stream5_IRQn = 68, 113 DMA2_Stream6_IRQn = 69, 114 DMA2_Stream7_IRQn = 70, 115 USART6_IRQn = 71, 116 I2C3_EV_IRQn = 72, 117 I2C3_ER_IRQn = 73, 118 OTG_HS_EP1_OUT_IRQn = 74, 119 OTG_HS_EP1_IN_IRQn = 75, 120 OTG_HS_WKUP_IRQn = 76, 121 OTG_HS_IRQn = 77, 122 DCMI_IRQn = 78, 123 CRYP_IRQn = 79, 124 HASH_RNG_IRQn = 80, 125 FPU_IRQn = 81, 126 NUM_INTERRUPTS 127 } IRQn_Type; 128 129 #include "core_cm4.h" 130 131 #ifdef __cplusplus 132 } 133 #endif 134 135 136 #endif 137 138
