1 // Copyright 2014 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_COMPILER_INSTRUCTION_CODES_H_ 6 #define V8_COMPILER_INSTRUCTION_CODES_H_ 7 8 #include <iosfwd> 9 10 #if V8_TARGET_ARCH_ARM 11 #include "src/compiler/arm/instruction-codes-arm.h" 12 #elif V8_TARGET_ARCH_ARM64 13 #include "src/compiler/arm64/instruction-codes-arm64.h" 14 #elif V8_TARGET_ARCH_IA32 15 #include "src/compiler/ia32/instruction-codes-ia32.h" 16 #elif V8_TARGET_ARCH_MIPS 17 #include "src/compiler/mips/instruction-codes-mips.h" 18 #elif V8_TARGET_ARCH_MIPS64 19 #include "src/compiler/mips64/instruction-codes-mips64.h" 20 #elif V8_TARGET_ARCH_X64 21 #include "src/compiler/x64/instruction-codes-x64.h" 22 #elif V8_TARGET_ARCH_PPC 23 #include "src/compiler/ppc/instruction-codes-ppc.h" 24 #elif V8_TARGET_ARCH_S390 25 #include "src/compiler/s390/instruction-codes-s390.h" 26 #elif V8_TARGET_ARCH_X87 27 #include "src/compiler/x87/instruction-codes-x87.h" 28 #else 29 #define TARGET_ARCH_OPCODE_LIST(V) 30 #define TARGET_ADDRESSING_MODE_LIST(V) 31 #endif 32 #include "src/utils.h" 33 34 namespace v8 { 35 namespace internal { 36 namespace compiler { 37 38 // Modes for ArchStoreWithWriteBarrier below. 39 enum class RecordWriteMode { kValueIsMap, kValueIsPointer, kValueIsAny }; 40 41 42 // Target-specific opcodes that specify which assembly sequence to emit. 43 // Most opcodes specify a single instruction. 44 #define COMMON_ARCH_OPCODE_LIST(V) \ 45 V(ArchCallCodeObject) \ 46 V(ArchTailCallCodeObjectFromJSFunction) \ 47 V(ArchTailCallCodeObject) \ 48 V(ArchCallJSFunction) \ 49 V(ArchTailCallJSFunctionFromJSFunction) \ 50 V(ArchTailCallJSFunction) \ 51 V(ArchTailCallAddress) \ 52 V(ArchPrepareCallCFunction) \ 53 V(ArchCallCFunction) \ 54 V(ArchPrepareTailCall) \ 55 V(ArchJmp) \ 56 V(ArchLookupSwitch) \ 57 V(ArchTableSwitch) \ 58 V(ArchNop) \ 59 V(ArchDebugBreak) \ 60 V(ArchComment) \ 61 V(ArchThrowTerminator) \ 62 V(ArchDeoptimize) \ 63 V(ArchRet) \ 64 V(ArchStackPointer) \ 65 V(ArchFramePointer) \ 66 V(ArchParentFramePointer) \ 67 V(ArchTruncateDoubleToI) \ 68 V(ArchStoreWithWriteBarrier) \ 69 V(CheckedLoadInt8) \ 70 V(CheckedLoadUint8) \ 71 V(CheckedLoadInt16) \ 72 V(CheckedLoadUint16) \ 73 V(CheckedLoadWord32) \ 74 V(CheckedLoadWord64) \ 75 V(CheckedLoadFloat32) \ 76 V(CheckedLoadFloat64) \ 77 V(CheckedStoreWord8) \ 78 V(CheckedStoreWord16) \ 79 V(CheckedStoreWord32) \ 80 V(CheckedStoreWord64) \ 81 V(CheckedStoreFloat32) \ 82 V(CheckedStoreFloat64) \ 83 V(ArchStackSlot) \ 84 V(AtomicLoadInt8) \ 85 V(AtomicLoadUint8) \ 86 V(AtomicLoadInt16) \ 87 V(AtomicLoadUint16) \ 88 V(AtomicLoadWord32) \ 89 V(AtomicStoreWord8) \ 90 V(AtomicStoreWord16) \ 91 V(AtomicStoreWord32) \ 92 V(Ieee754Float64Atan) \ 93 V(Ieee754Float64Atan2) \ 94 V(Ieee754Float64Atanh) \ 95 V(Ieee754Float64Cbrt) \ 96 V(Ieee754Float64Cos) \ 97 V(Ieee754Float64Exp) \ 98 V(Ieee754Float64Expm1) \ 99 V(Ieee754Float64Log) \ 100 V(Ieee754Float64Log1p) \ 101 V(Ieee754Float64Log10) \ 102 V(Ieee754Float64Log2) \ 103 V(Ieee754Float64Sin) \ 104 V(Ieee754Float64Tan) 105 106 #define ARCH_OPCODE_LIST(V) \ 107 COMMON_ARCH_OPCODE_LIST(V) \ 108 TARGET_ARCH_OPCODE_LIST(V) 109 110 enum ArchOpcode { 111 #define DECLARE_ARCH_OPCODE(Name) k##Name, 112 ARCH_OPCODE_LIST(DECLARE_ARCH_OPCODE) 113 #undef DECLARE_ARCH_OPCODE 114 #define COUNT_ARCH_OPCODE(Name) +1 115 kLastArchOpcode = -1 ARCH_OPCODE_LIST(COUNT_ARCH_OPCODE) 116 #undef COUNT_ARCH_OPCODE 117 }; 118 119 std::ostream& operator<<(std::ostream& os, const ArchOpcode& ao); 120 121 // Addressing modes represent the "shape" of inputs to an instruction. 122 // Many instructions support multiple addressing modes. Addressing modes 123 // are encoded into the InstructionCode of the instruction and tell the 124 // code generator after register allocation which assembler method to call. 125 #define ADDRESSING_MODE_LIST(V) \ 126 V(None) \ 127 TARGET_ADDRESSING_MODE_LIST(V) 128 129 enum AddressingMode { 130 #define DECLARE_ADDRESSING_MODE(Name) kMode_##Name, 131 ADDRESSING_MODE_LIST(DECLARE_ADDRESSING_MODE) 132 #undef DECLARE_ADDRESSING_MODE 133 #define COUNT_ADDRESSING_MODE(Name) +1 134 kLastAddressingMode = -1 ADDRESSING_MODE_LIST(COUNT_ADDRESSING_MODE) 135 #undef COUNT_ADDRESSING_MODE 136 }; 137 138 std::ostream& operator<<(std::ostream& os, const AddressingMode& am); 139 140 // The mode of the flags continuation (see below). 141 enum FlagsMode { 142 kFlags_none = 0, 143 kFlags_branch = 1, 144 kFlags_deoptimize = 2, 145 kFlags_set = 3 146 }; 147 148 std::ostream& operator<<(std::ostream& os, const FlagsMode& fm); 149 150 // The condition of flags continuation (see below). 151 enum FlagsCondition { 152 kEqual, 153 kNotEqual, 154 kSignedLessThan, 155 kSignedGreaterThanOrEqual, 156 kSignedLessThanOrEqual, 157 kSignedGreaterThan, 158 kUnsignedLessThan, 159 kUnsignedGreaterThanOrEqual, 160 kUnsignedLessThanOrEqual, 161 kUnsignedGreaterThan, 162 kFloatLessThanOrUnordered, 163 kFloatGreaterThanOrEqual, 164 kFloatLessThanOrEqual, 165 kFloatGreaterThanOrUnordered, 166 kFloatLessThan, 167 kFloatGreaterThanOrEqualOrUnordered, 168 kFloatLessThanOrEqualOrUnordered, 169 kFloatGreaterThan, 170 kUnorderedEqual, 171 kUnorderedNotEqual, 172 kOverflow, 173 kNotOverflow 174 }; 175 176 inline FlagsCondition NegateFlagsCondition(FlagsCondition condition) { 177 return static_cast<FlagsCondition>(condition ^ 1); 178 } 179 180 FlagsCondition CommuteFlagsCondition(FlagsCondition condition); 181 182 std::ostream& operator<<(std::ostream& os, const FlagsCondition& fc); 183 184 // The InstructionCode is an opaque, target-specific integer that encodes 185 // what code to emit for an instruction in the code generator. It is not 186 // interesting to the register allocator, as the inputs and flags on the 187 // instructions specify everything of interest. 188 typedef int32_t InstructionCode; 189 190 // Helpers for encoding / decoding InstructionCode into the fields needed 191 // for code generation. We encode the instruction, addressing mode, and flags 192 // continuation into a single InstructionCode which is stored as part of 193 // the instruction. 194 typedef BitField<ArchOpcode, 0, 8> ArchOpcodeField; 195 typedef BitField<AddressingMode, 8, 5> AddressingModeField; 196 typedef BitField<FlagsMode, 13, 2> FlagsModeField; 197 typedef BitField<FlagsCondition, 15, 5> FlagsConditionField; 198 typedef BitField<int, 20, 12> MiscField; 199 200 } // namespace compiler 201 } // namespace internal 202 } // namespace v8 203 204 #endif // V8_COMPILER_INSTRUCTION_CODES_H_ 205
