| /external/llvm/lib/Target/NVPTX/ |
| NVPTXRegisterInfo.cpp | 97 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
100 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegisterInfo.cpp | 62 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
64 int FrameOffset = MFI.getStackSize() + MFI.getObjectOffset(FrameIndex);
|
| /external/libopus/silk/ |
| dec_API.c | 271 opus_int FrameIndex;
274 FrameIndex = channel_state[ 0 ].nFramesDecoded - n;
276 if( FrameIndex <= 0 ) {
279 condCoding = channel_state[ n ].LBRR_flags[ FrameIndex - 1 ] ? CODE_CONDITIONALLY : CODE_INDEPENDENTLY;
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 114 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
117 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
|
| MSP430ISelDAGToDAG.cpp | 45 int FrameIndex;
71 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
196 case ISD::FrameIndex:
200 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
259 AM.Base.FrameIndex,
400 case ISD::FrameIndex: {
|
| MSP430ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 172 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
179 Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 71 int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
73 int64_t Offset = (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr) +
|
| SystemZISelDAGToDAG.cpp | 502 if (Base->getOpcode() == ISD::FrameIndex)
600 else if (Base.getOpcode() == ISD::FrameIndex) {
601 // Lower a FrameIndex to a TargetFrameIndex.
602 int64_t FrameIndex = cast<FrameIndexSDNode>(Base)->getIndex();
603 Base = CurDAG->getTargetFrameIndex(FrameIndex, VT);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 45 int FrameIndex;
69 MO.push_back(MachineOperand::CreateFI(Base.FrameIndex));
131 MIB.addFrameIndex(AM.Base.FrameIndex);
145 /// reference has base register as the FrameIndex offset until it is resolved.
|
| X86RegisterInfo.cpp | 543 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
551 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
553 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
568 Offset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
580 // FrameIndex with base register with EBP. Add an offset to the offset.
588 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
590 FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
|
| /external/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 44 ScavengedInfo(int FI = -1) : FrameIndex(FI), Reg(0), Restore(nullptr) {}
47 int FrameIndex;
124 if (I->FrameIndex == FI)
134 if (I->FrameIndex >= 0)
135 A.push_back(I->FrameIndex);
|
| WinEHFuncInfo.h | 68 int FrameIndex;
|
| ISDOpcodes.h | 62 GlobalAddress, GlobalTLSAddress, FrameIndex,
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.cpp | 259 // FrameIndex represent objects inside a abstract stack.
260 // We must replace FrameIndex with an stack/frame pointer
271 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
273 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
275 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
279 eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 267 int FrameIndex = FrameOp.getIndex();
274 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
282 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.cpp | 249 "Instr doesn't have FrameIndex operand!");
345 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
367 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
374 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
383 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);
387 assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 463 unsigned FrameIndex) const {
501 FrameIndex);
508 unsigned FrameIndex) const {
528 Reg), FrameIndex);
551 unsigned FrameIndex) const {
588 FrameIndex);
595 unsigned FrameIndex) const {
615 Reg), FrameIndex);
645 unsigned FrameIndex) const {
664 FrameIndex);
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DwarfDebug.h | 71 SmallVector<int, 1> FrameIndex; /// Frame index.
85 assert(FrameIndex.empty() && "Already initialized?");
92 FrameIndex.push_back(FI);
98 assert(FrameIndex.empty() && "Already initialized?");
120 ArrayRef<int> getFrameIndex() const { return FrameIndex; }
128 assert(!FrameIndex.empty() && "Expected an MMI entry");
129 assert(!V.FrameIndex.empty() && "Expected an MMI entry");
130 assert(Expr.size() == FrameIndex.size() && "Mismatched expressions");
131 assert(V.Expr.size() == V.FrameIndex.size() && "Mismatched expressions");
134 FrameIndex.append(V.FrameIndex.begin(), V.FrameIndex.end())
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegAllocFast.cpp | 634 int FrameIndex = getStackSpaceFor(VirtReg, RC);
637 TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI);
[all...] |
| TargetInstrInfo.cpp | 304 int &FrameIndex) const {
313 FrameIndex = Value->getFrameIndex();
324 int &FrameIndex) const {
333 FrameIndex = Value->getFrameIndex();
437 ArrayRef<unsigned> Ops, int FrameIndex,
483 MIB.addFrameIndex(FrameIndex);
790 int FrameIndex = 0;
794 isLoadFromStackSlot(LoadMI, FrameIndex)) {
796 NewMI = foldPatchpoint(MF, MI, Ops, FrameIndex, *this);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 478 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
597 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
618 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
691 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
694 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
701 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 189 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
[all...] |
| AMDGPUISelLowering.cpp | 621 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
