| /external/llvm/lib/Target/NVPTX/ |
| NVPTXTargetTransformInfo.cpp | 99 int ISD = TLI->InstructionOpcodeToISD(Opcode);
101 switch (ISD) {
105 case ISD::ADD:
106 case ISD::MUL:
107 case ISD::XOR:
108 case ISD::OR:
109 case ISD::AND:
|
| /external/llvm/include/llvm/Target/ |
| CostTable.h | 25 int ISD;
32 int ISD, MVT Ty) {
35 return ISD == Entry.ISD && Ty == Entry.Type; });
45 int ISD;
55 int ISD, MVT Dst, MVT Src) {
58 return ISD == Entry.ISD && Src == Entry.Src &&
|
| TargetCallingConv.h | 25 namespace ISD {
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 51 int ISD = TLI->InstructionOpcodeToISD(Opcode);
52 assert(ISD && "Invalid opcode");
57 { ISD::FP_ROUND, MVT::v2f64, 2 },
58 { ISD::FP_EXTEND, MVT::v2f32, 2 },
59 { ISD::FP_EXTEND, MVT::v4f32, 4 }
62 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
63 ISD == ISD::FP_EXTEND)) {
65 if (const auto *Entry = CostTableLookup(NEONFltDblTbl, ISD, LT.second)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCTargetTransformInfo.cpp | 297 int ISD = TLI->InstructionOpcodeToISD(Opcode);
298 assert(ISD && "Invalid opcode");
319 if (ISD == ISD::INSERT_VECTOR_ELT)
326 if (ISD == ISD::EXTRACT_VECTOR_ELT ||
327 ISD == ISD::INSERT_VECTOR_ELT)
|
| /external/clang/test/CXX/temp/temp.spec/temp.expl.spec/ |
| examples.cpp | 231 namespace ISD {
233 template class BasicStringPiece<int>; // expected-error {{explicit instantiation of undefined template 'spec_vs_expl_inst::ISD::BasicStringPiece<int>'}}
|
| /external/llvm/lib/MC/ |
| MCELFStreamer.cpp | 195 IndirectSymbolData ISD;
196 ISD.Symbol = Symbol;
197 ISD.Section = getCurrentSectionOnly();
198 getAssembler().getIndirectSymbols().push_back(ISD);
|
| MCMachOStreamer.cpp | 285 IndirectSymbolData ISD;
286 ISD.Symbol = Symbol;
287 ISD.Section = getCurrentSectionOnly();
288 getAssembler().getIndirectSymbols().push_back(ISD);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 180 int ISD = TLI->InstructionOpcodeToISD(Opcode);
181 assert(ISD && "Invalid opcode");
191 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
192 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
193 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
194 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
197 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
198 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
199 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
200 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| BasicTTIImpl.h | 183 return TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
184 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
191 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT);
293 int ISD = TLI->InstructionOpcodeToISD(Opcode);
294 assert(ISD && "Invalid opcode");
303 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
309 if (!TLI->isOperationExpand(ISD, LT.second)) {
340 int ISD = TLI->InstructionOpcodeToISD(Opcode);
341 assert(ISD && "Invalid opcode");
364 TLI->isOperationLegalOrPromote(ISD, DstLT.second)
[all...] |
| SelectionDAGNodes.h | 66 namespace ISD {
86 /// and all operands of the specified node are ISD::UNDEF.
88 } // end llvm:ISD namespace
439 /// are the opcode values in the ISD and <target>ISD namespaces. For
444 /// \<target\>ISD namespace).
445 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
448 /// memory-referencing opcode (in the \<target\>ISD namespace and
451 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
455 bool isUndef() const { return NodeType == ISD::UNDEF;
[all...] |
| ISDOpcodes.h | 19 /// ISD namespace - This namespace contains an enum which represents all of the
22 namespace ISD {
25 /// ISD::NodeType enum - This enum defines the target-independent operators
502 /// 5) ISD::CvtCode indicating the type of conversion to do
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 95 int ISD = TLI->InstructionOpcodeToISD(Opcode);
96 assert(ISD && "Invalid opcode");
98 if (ISD == ISD::SDIV &&
119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle.
121 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
122 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence
123 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
124 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence
129 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD,
[all...] |
