| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyMCInstLower.cpp | 84 const ConstantFP *Imm = MO.getFPImm();
85 if (Imm->getType()->isFloatTy())
86 MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToFloat());
87 else if (Imm->getType()->isDoubleTy())
88 MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToDouble());
|
| /external/llvm/lib/Target/NVPTX/InstPrinter/ |
| NVPTXInstPrinter.cpp | 85 O << markup("<imm:") << formatImm(Op.getImm()) << markup(">");
95 int64_t Imm = MO.getImm();
99 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG)
103 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG)
107 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) {
145 int64_t Imm = MO.getImm();
149 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG)
152 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) {
219 int Imm = (int) MO.getImm();
221 if (Imm)
[all...] |
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 89 static uint32_t getIntInlineImmEncoding(IntTy Imm) {
90 if (Imm >= 0 && Imm <= 64)
91 return 128 + Imm;
93 if (Imm >= -16 && Imm <= -1)
94 return 192 + std::abs(Imm);
212 int64_t Imm = 0;
215 Imm = Op.getImm();
220 OS.write((uint8_t) ((Imm >> (8 * j)) & 0xff))
[all...] |
| /external/llvm/lib/Target/BPF/MCTargetDesc/ |
| BPFMCCodeEmitter.cpp | 128 uint64_t Imm = MO.isImm() ? MO.getImm() : 0;
133 LE.write<uint32_t>(Imm >> 32);
135 BE.write<uint32_t>(Imm >> 32);
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 74 int64_t Imm = MI->getOperand(Op).getImm();
75 switch (Imm) {
114 int64_t Imm = MI->getOperand(Op).getImm();
115 switch (Imm) {
130 int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
131 switch (Imm) {
169 O << markup("<imm:") << '$' << formatImm((int64_t)Op.getImm())
177 *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
181 O << markup("<imm:") << '$';
221 O << ',' << markup("<imm:") << ScaleVal // never printed in hex
[all...] |
| X86IntelInstPrinter.cpp | 56 int64_t Imm = MI->getOperand(Op).getImm();
57 switch (Imm) {
96 int64_t Imm = MI->getOperand(Op).getImm();
97 switch (Imm) {
112 int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
113 switch (Imm) {
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonInstPrinter.cpp | 131 int64_t Imm;
132 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
133 Imm = SignExtend64<9>(Imm);
135 assert(((Imm & 0x3f) == 0) && "Lower 6 bits must be ZERO.");
136 O << formatImm(Imm/64);
141 int64_t Imm;
142 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
143 Imm = SignExtend64<10>(Imm);
[all...] |
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 218 // Encode (imm, reg) as a memri, which has the low 16-bits as the
237 // Encode (imm, reg) as a memrix, which has the low 14-bits as the
257 // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8)
264 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;
265 return reverseBits(Imm | RegBits) >> 22;
273 // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4)
280 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;
281 return reverseBits(Imm | RegBits) >> 22
[all...] |
| /external/llvm/utils/TableGen/ |
| PseudoLoweringEmitter.cpp | 28 enum MapKind { Operand, Imm, Reg };
32 uint64_t Imm; // Integer immedate value.
105 OperandMap[BaseIdx + i].Kind = OpData::Imm;
106 OperandMap[BaseIdx + i].Data.Imm = II->getValue();
234 case OpData::Imm:
236 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
|
| CodeGenInstruction.h | 311 int64_t Imm;
320 ResultOperand(int64_t I) : Imm(I), Kind(K_Imm) {}
329 int64_t getImm() const { assert(isImm()); return Imm; }
|
| /external/llvm/lib/CodeGen/ |
| StackMaps.cpp | 103 int64_t Imm = (++MOI)->getImm();
105 getDwarfRegNum(Reg, TRI), Imm);
112 int64_t Imm = (++MOI)->getImm();
114 getDwarfRegNum(Reg, TRI), Imm);
120 int64_t Imm = MOI->getImm();
121 Locs.emplace_back(Location::Constant, sizeof(int64_t), 0, Imm);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 198 int64_t Imm = MO.getImm();
199 O << '#' << Imm;
|
| AArch64ConditionOptimizer.cpp | 254 int Imm;
257 std::tie(Imm, Opc, Cmp) = Info;
265 .addImm(Imm)
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIFoldOperands.cpp | 179 // One of operands might be an Imm operand, and OpNo may refer to it after
214 APInt Imm;
223 Imm = APInt(64, OpToFold.getImm());
235 Imm = Imm.getLoBits(32);
238 Imm = Imm.getHiBits(32);
290 MachineOperand ImmOp = MachineOperand::CreateImm(Imm.getSExtValue());
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 106 // reg [asr|lsl|lsr|ror|rrx] imm
109 // reg, the second is the shift amount (or reg0 if not present or imm). The
110 // third operand encodes the shift opcode and the imm if a reg isn't present.
112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
113 return ShOp | (Imm << 3);
122 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
123 /// the 8-bit imm value.
124 static inline unsigned getSOImmValImm(unsigned Imm) {
125 return Imm & 0xFF
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 195 const MCOperand &Imm, int AlignSize) {
198 if (Imm.getExpr()->evaluateAsAbsolute(Value)) {
228 assert(Imm.isExpr() && "Expected expression and found none");
252 OutStreamer.EmitValue(Imm.getExpr(), AlignSize);
271 const MCOperand &Imm = MappedInst.getOperand(1);
274 MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 8);
292 MCOperand &Imm = MappedInst.getOperand(1);
294 MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 4);
367 int64_t Imm;
369 bool Success = Expr->evaluateAsAbsolute(Imm);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 606 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
607 int Offset = FIOffset + Imm;
608 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
|
| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 194 /// IMM = bits{8}
245 } Imm;
248 Imm.f = MO.getFPImm();
249 Value |= ((uint64_t)Imm.i) << 32;
|
| /external/v8/test/unittests/compiler/ |
| instruction-sequence-unittest.cc | 143 InstructionSequenceTest::TestOperand InstructionSequenceTest::Imm(int32_t imm) {
144 return TestOperand(kImmediate, imm);
201 int32_t imm) {
203 sequence()->AddConstant(vreg.value_, Constant(imm));
300 InstructionOperand inputs[4]{ConvertInputOp(input_op), ConvertInputOp(Imm()),
301 ConvertInputOp(Imm()), ConvertInputOp(Imm())};
316 InstructionOperand inputs[1]{ConvertInputOp(Imm())};
|
| /external/llvm/lib/IR/ |
| AutoUpgrade.cpp | 437 unsigned Imm;
439 Imm = 0;
441 Imm = 1;
443 Imm = 2;
445 Imm = 3;
447 Imm = 4;
449 Imm = 5;
451 Imm = 6;
453 Imm = 7;
460 Builder.getInt8(Imm)});
[all...] |
| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 83 uint16_t Imm = MI->getOperand(OpNo).getImm();
84 if (Imm != 0) {
232 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, raw_ostream &O) {
233 int32_t SImm = static_cast<int32_t>(Imm);
239 if (Imm == FloatToBits(0.0f))
241 else if (Imm == FloatToBits(1.0f))
243 else if (Imm == FloatToBits(-1.0f))
245 else if (Imm == FloatToBits(0.5f))
247 else if (Imm == FloatToBits(-0.5f))
249 else if (Imm == FloatToBits(2.0f)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelLowering.cpp | 733 int64_t imm = MI->getOperand(1).getImm(); local
736 if (isUInt<8>(imm))
738 else if ((!ImmSigned && isUInt<16>(imm)) ||
739 (ImmSigned && isInt<16>(imm)))
744 .addImm(imm);
751 (unsigned shortOp, unsigned longOp, int64_t Imm) {
752 if (isUInt<8>(Imm))
754 else if (isInt<16>(Imm))
786 int64_t Imm = MI->getOperand(2).getImm();
787 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
[all...] |
| /external/llvm/tools/llvm-readobj/ |
| ARMWinEHPrinter.cpp | 226 uint8_t Imm = OC[Offset] & 0x7f;
230 Imm);
316 uint16_t Imm = ((OC[Offset + 0] & 0x03) << 8) | ((OC[Offset + 1] & 0xff) << 0);
321 Imm);
405 uint32_t Imm = (OC[Offset + 1] << 8) | (OC[Offset + 2] << 0);
410 Imm);
418 uint32_t Imm = (OC[Offset + 1] << 16)
425 static_cast<const char *>(Prologue ? "sub" : "add"), Imm);
433 uint32_t Imm = (OC[Offset + 1] << 8) | (OC[Offset + 2] << 0);
438 static_cast<const char *>(Prologue ? "sub" : "add"), Imm);
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 83 static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
86 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
89 static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
91 static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
93 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
95 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
147 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
149 static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
152 static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm,
154 static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
806 unsigned imm = fieldFromInstruction(insn, 5, 16); local
1356 unsigned imm; local
1386 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; local
1425 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; local
1441 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; local
1496 int64_t imm = fieldFromInstruction(insn, 0, 26); local
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | [all...] |
