| /external/v8/src/crankshaft/arm64/ |
| delayed-masm-arm64-inl.h | 23 void DelayedMasm::Mov(const Register& rd,
28 __ Mov(rd, operand, discard_mode);
|
| /external/llvm/lib/Target/AMDGPU/ |
| R600ExpandSpecialInstrs.cpp | 86 MachineInstr *Mov = TII->buildMovInstr(&MBB, I,
91 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(),
94 Mov->getOperand(MovPredSelIdx).setReg(
|
| R600InstrInfo.cpp | 67 buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
74 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
98 case AMDGPU::MOV:
[all...] |
| /art/compiler/utils/arm/ |
| assembler_arm32.cc | 148 void Arm32Assembler::mov(Register rd, const ShifterOperand& so, function in class:art::arm::Arm32Assembler
150 EmitType01(cond, so.type(), MOV, set_cc, R0, rd, so);
682 static_cast<int32_t>(MOV) << kOpcodeShift |
699 static_cast<int32_t>(MOV) << kOpcodeShift |
[all...] |
| assembler_thumb2.cc | 532 case MOV:
624 void Thumb2Assembler::mov(Register rd, const ShifterOperand& so, function in class:art::arm::Thumb2Assembler
626 EmitDataProcessing(cond, MOV, set_cc, R0, rd, so);
[all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | 219 Mov(rd, -operand.ImmediateValue());
290 Mov(rd, ~imm);
772 Mov(tmp, float_to_rawbits(imm));
956 void MacroAssembler::Mov(const Register& rd, const Register& rn) {
960 // not X registers. Note that mov(w0, w0) is not a no-op because it clears
963 Assembler::mov(rd, rn);
[all...] |
| macro-assembler-arm64.cc | 90 Mov(rd, 0);
94 Mov(rd, rn);
106 Mov(rd, rn);
109 Mov(rd, immediate);
134 Mov(csp, temp);
161 void MacroAssembler::Mov(const Register& rd, uint64_t imm) {
203 // Mov instructions can't move immediate values into the stack pointer, so
233 mov(rd, temp);
240 void MacroAssembler::Mov(const Register& rd,
256 Mov(dst, operand.ImmediateValue())
[all...] |
| /external/vixl/src/vixl/a64/ |
| macro-assembler-a64.cc | 364 // The worst case for size is mov 64-bit immediate to sp:
407 // Mov instructions can't move values into the stack pointer, so set up a
445 if (emit_code) masm->mov(rd, temp);
739 Mov(rd, 0);
744 Mov(rd, rn);
757 Mov(rd, rn);
760 Mov(rd, immediate);
787 Mov(sp, temp);
813 void MacroAssembler::Mov(const Register& rd,
817 // The worst case for size is mov immediate with up to 4 instructions
[all...] |
| macro-assembler-a64.h | 594 // instruction using 'mov immediate' instructions. A user might prefer loading
595 // a constant using the literal pool instead of using multiple 'mov immediate'
688 void Mov(const Register& rd, uint64_t imm);
689 void Mov(const Register& rd,
693 Mov(rd, (rd.size() == kXRegSize) ? ~imm : (~imm & kWRegMask));
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 800 MachineInstrBuilder Mov;
818 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
821 Mov.addReg(Src);
822 Mov = AddDefaultPred(Mov);
825 Mov = AddDefaultCC(Mov);
828 Mov->addRegisterDefined(DestReg, TRI);
830 Mov->addRegisterKilled(SrcReg, TRI);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/valgrind/VEX/priv/ |
| host_arm_defs.h | 657 /* MOV dst, src -- reg-reg (or reg-imm8x4) move */
661 } Mov;
719 /* Mov src to dst on the given condition, which may not
806 /* 64-bit FP mov src to dst on the given condition, which may
813 /* 32-bit FP mov src to dst on the given condition, which may
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
