| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypesGeneric.cpp | 225 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT);
238 NewVT, 2*OldElts),
245 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx);
249 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx);
385 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT);
407 NewVT, NewElts.size()),
|
| LegalizeVectorOps.cpp | 473 EVT NewVT;
476 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
477 assert(NewVT.isSimple() && "Promoting to a non-simple vector type!");
478 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
482 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
489 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
[all...] |
| LegalizeVectorTypes.cpp | 167 EVT NewVT = N->getValueType(0).getVectorElementType();
169 NewVT, N->getOperand(0));
183 EVT NewVT = N->getValueType(0).getVectorElementType();
185 return DAG.getConvertRndSat(NewVT, SDLoc(N),
186 Op0, DAG.getValueType(NewVT),
200 EVT NewVT = N->getValueType(0).getVectorElementType();
203 NewVT, Op, N->getOperand(1));
[all...] |
| SelectionDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCalls.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
