/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p2/src/ |
omxVCM4P2_MCReconBlock_s.s | 298 LCLS OP1 301 OP1 SETS "AND" 304 OP1 SETS "ORR" 316 $OP1 $lsb0, $lsb0, $lsb1 ;// e0 = e0 & e1
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/external/mesa3d/src/gallium/state_trackers/d3d1x/gd3d1x/ |
sm4_to_tgsi.cpp | 239 #define OP1(n) OP1_(n, n) 258 OP1(MOV); 265 OP1(FRC); 266 OP1(RCP); 275 OP1(NOT); 284 OP1(RSQ); 495 OP1(INEG);
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/external/valgrind/VEX/test/ |
test-amd64.c | 97 #define OP1 102 #define OP1 107 #define OP1 112 #define OP1 368 void test_imulw2(int64 op0, int64 op1) 372 s1 = op1; 386 void test_imull2(int64 op0, int64 op1) 391 s1 = op1; 405 #define TEST_IMUL_IM(size, size1, op0, op1)\ 416 : "r" (op1), "1" (flags), "0" (res)); [all...] |
test-i386.c | 87 #define OP1 92 #define OP1 97 #define OP1 102 #define OP1 356 void test_imulw2(int op0, int op1) 360 s1 = op1; 374 void test_imull2(int op0, int op1) 378 s1 = op1; 392 #define TEST_IMUL_IM(size, size1, op0, op1)\ 403 : "r" (op1), "1" (flags), "0" (res)); [all...] |
/toolchain/binutils/binutils-2.25/include/opcode/ |
tic6x-opcode-table.h | 42 #define OP1(a) 1, { a } 496 OP1(OLCST), 500 OP1(ORXREG1), 504 OP1(ORIRP1), 508 OP1(ORNRP1), 580 OP1(OLCST), 585 OP1(ORXREG1), 590 OP1(ORIRP1), 595 OP1(ORNRP1), 632 OP1(OLCST) [all...] |
/external/llvm/lib/Target/AMDGPU/ |
R600Defines.h | 41 OP1 = (1 << 10),
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/external/llvm/lib/Target/Hexagon/ |
HexagonISelDAGToDAG.cpp | 626 SDValue OP1; 661 OP1 = Sext1; 672 OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32, 682 OP0, OP1); [all...] |
/toolchain/binutils/binutils-2.25/opcodes/ |
aarch64-tbl.h | 28 #define OP1(a) {OPND(a)} 55 /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */ 61 /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */ [all...] |
/external/pcre/dist/ |
pcre_jit_compile.c | 519 #define OP1(op, dst, dstw, src, srcw) \ [all...] |