| /external/llvm/utils/TableGen/ |
| AsmWriterInst.h | 11 // the string into operands, which can be literal strings (the constant bits of
12 // the string), actual operands (i.e., operands from the MachineInstr), and
93 std::vector<AsmWriterOperand> Operands;
108 if (!Operands.empty() &&
109 Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand)
110 Operands.back().Str.append(Str);
112 Operands.push_back(AsmWriterOperand(Str));
|
| DAGISelMatcher.cpp | 273 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
274 OS << Operands[i] << ' ';
336 M->Operands == Operands && M->HasChain == HasChain &&
343 return (HashString(OpcodeName) << 4) | Operands.size();
|
| DAGISelMatcherOpt.cpp | 142 const SmallVectorImpl<unsigned> &Operands = EN->getOperandList();
144 VTs, Operands,
|
| X86RecognizableInstr.h | 63 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
97 /// The operands of the instruction, as listed in the CodeGenInstruction.
98 /// They are not one-to-one with operands listed in the MCInst; for example,
99 /// memory operands expand to 5 operands in the MCInst
100 const std::vector<CGIOperandList::OperandInfo>* Operands;
118 /// prefix. If it does, 32-bit register operands stay
133 /// If it is not, then 16-bit immediate operands stay 16-bit.
139 /// handles operands that are in the REG field of the ModR/M byte.
144 /// handles operands that are in the REG field of the ModR/M byte
[all...] |
| InstrInfoEmitter.cpp | 64 std::map<std::string, unsigned> &Operands,
91 for (auto &Op : Inst.Operands) {
92 // Handle aggregate operands and normal operands the same way by expanding
93 // either case into a list of operands for this op.
97 // registers in their multi-operand operands. It may also be an anonymous
135 // Predicate operands. Check to see if the original unexpanded operand
140 // Optional def operands. Check to see if the original unexpanded operand
195 /// \param Operands [out] A map used to generate the OpName enum with operand
203 std::map<std::string, unsigned> &Operands,
[all...] |
| CodeGenInstruction.h | 74 /// PrinterMethodName - The method used to print operands of this type in
87 /// operands correspond to multiple MachineInstr operands. In the X86
93 unsigned MINumOperands; // The number of operands.
101 /// up of multiple MI operands.
131 /// NumDefs - Number of def operands declared, this is the number of
136 /// OperandList - The list of declared operands, along with their declared
173 /// to operands with suboperands are allowed, otherwise not.
216 /// Operands - This is information about the (ins) and (outs) list specified
218 CGIOperandList Operands;
[all...] |
| FixedLenDecoderEmitter.cpp | 315 const std::map<unsigned, std::vector<OperandInfo> > &Operands;
345 : AllInstructions(Insts), Opcodes(IDs), Operands(Ops), Filters(),
356 : AllInstructions(Insts), Opcodes(IDs), Operands(Ops),
556 Owner->Operands, BitValueArray, *Owner)));
583 Owner->Operands, BitValueArray, *Owner)));
[all...] |
| AsmMatcherEmitter.cpp | 11 // assembly operands in the MCInst structures. It also emits a matcher for
14 // Converting assembly operands into MCInst structures
18 // operands. The target specific parser should generally eliminate any syntax
22 // operands.
59 // arbitrary operands, we expect the user to define the classes and their
63 // By partitioning the operands in this way, we guarantee that for any
65 // of the sets of operands which could classify to that tuple.
78 // Some targets need a custom way to parse operands, some specific instructions
147 /// class of operands which can be matched.
170 /// sake user operands only record their immediate super class, while registe
[all...] |
| DAGISelMatcher.h | [all...] |
| /external/llvm/lib/Analysis/ |
| ScalarEvolutionNormalization.cpp | 109 SmallVector<const SCEV *, 8> Operands;
111 // The addrec conceptually uses its operands at loop entry.
116 Operands.push_back(TransformSubExpr(*I, LUser, nullptr));
119 const SCEV *Result = SE.getAddRecExpr(Operands, L, SCEV::FlagAnyWrap);
191 SmallVector<const SCEV *, 8> Operands;
199 Operands.push_back(N);
204 case scAddExpr: return SE.getAddExpr(Operands);
205 case scMulExpr: return SE.getMulExpr(Operands);
206 case scSMaxExpr: return SE.getSMaxExpr(Operands);
207 case scUMaxExpr: return SE.getUMaxExpr(Operands);
[all...] |
| ScalarEvolution.cpp | 522 // Compare the number of operands.
677 // Keep looking at all operands of S.
729 for (const SCEV *Op : T->operands()) {
803 for (const SCEV *Op : Numerator->operands()) {
830 for (const SCEV *Op : Numerator->operands()) {
840 // Check whether Denominator divides one of the product operands.
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCBoolRetToInt.cpp | 70 for (auto &Op : CurrUser->operands())
83 // Temporarily set the operands to 0. We'll fix this later in
108 // 3. All of its operands are Constant or Argument or
111 // 5. All of its PHINode operands are Promotable
133 const auto &Operands = P->operands();
135 !std::all_of(Operands.begin(), Operands.end(), IsValidOperand))
152 const auto &Operands = P->operands();
[all...] |
| /external/llvm/lib/Transforms/IPO/ |
| StripSymbols.cpp | 144 SmallPtrSet<Constant*, 4> Operands;
145 for (Value *Op : C->operands())
147 Operands.insert(cast<Constant>(Op));
157 for (Constant *O : Operands)
|
| ArgumentPromotion.cpp | 21 // more than three operands to the function, because passing thousands of
22 // operands for a large array or structure is unprofitable! This limit can be
386 // This load is safe if any prefix of its operands is safe to load.
503 IndicesVector Operands;
506 Operands.clear();
512 Operands.push_back(0);
528 Operands.push_back(C->getSExtValue());
547 // is safe if Operands, or a prefix of Operands, is marked as safe.
548 if (!PrefixIn(Operands, SafeToUnconditionallyLoad)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 77 // Operands are allocated by an ArrayRecycler.
78 MachineOperand *Operands; // Pointer to the first operand.
79 unsigned NumOperands; // Number of operands on instruction.
81 OperandCapacity CapOperands; // Capacity of the Operands array.
113 /// This constructor create a MachineInstr and add the implicit operands.
114 /// It reserves space for number of operands specified by
272 /// Access to explicit operands of the instruction.
278 return Operands[i];
282 return Operands[i];
285 /// Returns the number of non-implicit operands
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCInst.h | 31 /// \brief Instances of this class represent operands of the MCInst class.
153 SmallVector<MCOperand, 8> Operands;
164 const MCOperand &getOperand(unsigned i) const { return Operands[i]; }
165 MCOperand &getOperand(unsigned i) { return Operands[i]; }
166 unsigned getNumOperands() const { return Operands.size(); }
168 void addOperand(const MCOperand &Op) { Operands.push_back(Op); }
172 void clear() { Operands.clear(); }
173 void erase(iterator I) { Operands.erase(I); }
174 size_t size() const { return Operands.size(); }
175 iterator begin() { return Operands.begin();
[all...] |
| /external/llvm/lib/DebugInfo/DWARF/ |
| DWARFDebugFrame.cpp | 64 /// opcode and an optional sequence of operands.
65 typedef std::vector<uint64_t> Operands;
72 Operands Ops;
78 /// operands to the Instructions vector.
129 // No operands
133 // Operands: Address
137 // Operands: 1-byte delta
141 // Operands: 2-byte delta
145 // Operands: 4-byte delta
153 // Operands: ULEB12
[all...] |
| /external/llvm/lib/IR/ |
| ConstantsContext.h | 56 // allocate space for exactly two operands
77 // allocate space for exactly three operands
98 // allocate space for exactly two operands
119 // allocate space for exactly three operands
141 // allocate space for exactly three operands
268 // allocate space for exactly two operands
369 ArrayRef<Constant *> Operands;
370 ConstantAggrKeyType(ArrayRef<Constant *> Operands) : Operands(Operands) {}
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| ScalarEvolutionExpressions.h | 141 const SCEV *const *Operands;
146 : SCEV(ID, T), Operands(O), NumOperands(N) {}
152 return Operands[i];
157 op_iterator op_begin() const { return Operands; }
158 op_iterator op_end() const { return Operands + NumOperands; }
159 op_range operands() const {
287 /// All operands of an AddRec are required to be loop invariant.
299 const SCEV *getStart() const { return Operands[0]; }
585 SmallVector<const SCEV *, 2> Operands;
587 Operands.push_back(((SC*)this)->visit(Expr->getOperand(i)))
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600InstrInfo.cpp | 599 assert (Consts.size() <= 12 && "Too many operands in instructions group");
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| SCCP.cpp | 431 // because they have potentially new operands.
676 // Look at all of the executable operands of the PHI node. If any of them
680 // If there are no executable operands, the PHI remains undefined.
871 // Otherwise, one of our operands is overdefined. Try to produce something
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILPeepholeOptimizer.cpp | 663 Value *Operands[4] = {
669 CallInst *CI = CallInst::Create(Func, Operands, "BitInsertOpt");
828 Value *Operands[3] = {
833 // Lets create the Call with the operands
834 CallInst *CI = CallInst::Create(Func, Operands, "ByteExtractOpt");
[all...] |
| /external/google-breakpad/src/common/dwarf/ |
| dwarf2reader.cc | [all...] |
| /external/llvm/include/llvm/IR/ |
| Metadata.h | 168 /// This allows, e.g., instrinsics to have metadata as operands.
361 /// operands could refer to any \a Value. There's was a lot of code like this:
736 /// unresolved. As soon as all operands become resolved, it will drop RAUW
812 /// support (because all operands are resolved).
815 /// resolved automatically. However, if this (or one of its operands) is
838 /// \pre No operands (or operands' operands, etc.) have \a isTemporary().
938 op_range operands() const { return op_range(op_begin(), op_end()); } function in class:llvm::MDNode
945 /// \brief Return number of MDNode operands
1215 inline iterator_range<op_iterator> operands() { function in class:llvm::NamedMDNode
1218 inline iterator_range<const_op_iterator> operands() const { function in class:llvm::NamedMDNode
[all...] |
| /external/llvm/lib/CodeGen/MIRParser/ |
| MIParser.cpp | 53 "Only used register operands can be tied");
191 ArrayRef<ParsedMachineOperand> Operands);
193 bool verifyImplicitOperands(ArrayRef<ParsedMachineOperand> Operands,
569 // Parse any register operands before '='
571 SmallVector<ParsedMachineOperand, 8> Operands;
577 Operands.push_back(
583 if (!Operands.empty() && expectAndConsume(MIToken::equal))
590 // Parse the remaining machine operands.
597 Operands.push_back(
618 // Parse the machine memory operands
[all...] |
