| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 93 SmallVector<ISD::OutputArg, 4> Outs;
94 GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI,
97 Fn->isVarArg(), Outs, Fn->getContext());
|
| FastISel.cpp | [all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 258 auto &Outs = CLI.Outs;
283 CCInfo.AnalyzeCallOperands(Outs, CC_BPF64);
287 if (Outs.size() >= 6) {
293 for (auto &Arg : Outs) {
389 const SmallVectorImpl<ISD::OutputArg> &Outs,
407 CCInfo.AnalyzeReturn(Outs, RetCC_BPF64);
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 346 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
347 for (const ISD::OutputArg &Out : Outs) {
463 const SmallVectorImpl<ISD::OutputArg> &Outs,
466 return Outs.size() <= 1;
471 const SmallVectorImpl<ISD::OutputArg> &Outs,
474 assert(Outs.size() <= 1 && "WebAssembly can only return up to one value");
483 for (const ISD::OutputArg &Out : Outs) {
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 265 const SmallVectorImpl<ISD::OutputArg> &Outs) {
266 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
350 const SmallVectorImpl<ISD::OutputArg> &Outs) {
351 State.AnalyzeReturn(Outs, RetCC_MSP430);
394 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
412 Outs, OutVals, Ins, dl, DAG, InVals);
523 const SmallVectorImpl<ISD::OutputArg> &Outs,
531 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
539 AnalyzeReturnValues(CCInfo, RVLocs, Outs);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 81 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 794 static void VerifyVectorTypes(const SmallVectorImpl<ISD::OutputArg> &Outs) {
795 for (unsigned i = 0; i < Outs.size(); ++i)
796 VerifyVectorType(Outs[i].VT, Outs[i].ArgVT);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | [all...] |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | [all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 559 const SmallVectorImpl<ISD::OutputArg> &Outs,
571 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
648 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
658 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
682 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
684 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
695 Outs, OutVals, Ins, DAG);
722 ISD::ArgFlagsTy Flags = Outs[i].Flags
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 196 const SmallVectorImpl<ISD::OutputArg> &Outs,
200 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
201 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
207 const SmallVectorImpl<ISD::OutputArg> &Outs,
220 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
292 const SmallVectorImpl<ISD::OutputArg> &Outs,
303 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
739 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
755 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
