| /external/llvm/lib/Target/AArch64/ |
| AArch64PBQPRegAlloc.cpp | 159 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd,
161 if (Rd == Ra)
166 if (TRI->isPhysicalRegister(Rd) || TRI->isPhysicalRegister(Ra)) {
167 DEBUG(dbgs() << "Rd is a physical reg:" << TRI->isPhysicalRegister(Rd)
174 PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd);
187 const LiveInterval &ld = LIs.getInterval(Rd);
243 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd,
249 if (Rd != Ra) {
251 << PrintReg(Rd, TRI) << '\n';)
[all...] |
| /prebuilts/go/darwin-x86/src/crypto/md5/ |
| md5block_arm.s | 15 #define Rd R5 // MD5 accumulator
65 MOVM.IA (Rc0), [Ra,Rb,Rc,Rd]
69 #define ROUND1(Ra, Rb, Rc, Rd, index, shift, Rconst) \
70 EOR Rc, Rd, Rt0 ; \
72 EOR Rd, Rt0 ; \
80 ROUND1(Ra, Rb, Rc, Rd, 0, 7, Rc0)
81 ROUND1(Rd, Ra, Rb, Rc, 1, 12, Rc1)
82 ROUND1(Rc, Rd, Ra, Rb, 2, 17, Rc2)
83 ROUND1(Rb, Rc, Rd, Ra, 3, 22, Rc3)
86 ROUND1(Ra, Rb, Rc, Rd, 4, 7, Rc0
[all...] |
| /prebuilts/go/linux-x86/src/crypto/md5/ |
| md5block_arm.s | 15 #define Rd R5 // MD5 accumulator
65 MOVM.IA (Rc0), [Ra,Rb,Rc,Rd]
69 #define ROUND1(Ra, Rb, Rc, Rd, index, shift, Rconst) \
70 EOR Rc, Rd, Rt0 ; \
72 EOR Rd, Rt0 ; \
80 ROUND1(Ra, Rb, Rc, Rd, 0, 7, Rc0)
81 ROUND1(Rd, Ra, Rb, Rc, 1, 12, Rc1)
82 ROUND1(Rc, Rd, Ra, Rb, 2, 17, Rc2)
83 ROUND1(Rb, Rc, Rd, Ra, 3, 22, Rc3)
86 ROUND1(Ra, Rb, Rc, Rd, 4, 7, Rc0
[all...] |
| /prebuilts/go/darwin-x86/src/crypto/sha1/ |
| sha1block_arm.s | 31 #define Rd R5 // SHA1 accumulator
83 #define FUNC1(Ra, Rb, Rc, Rd, Re) \
86 AND Rd, Rt1, Rt1 ; \
90 #define FUNC2(Ra, Rb, Rc, Rd, Re) \
92 EOR Rd, Rt1, Rt1
96 #define FUNC3(Ra, Rb, Rc, Rd, Re) \
99 AND Rd, Rt0, Rt0 ; \
107 #define MIX(Ra, Rb, Rc, Rd, Re) \
113 #define ROUND1(Ra, Rb, Rc, Rd, Re) \
115 FUNC1(Ra, Rb, Rc, Rd, Re) ;
[all...] |
| /prebuilts/go/linux-x86/src/crypto/sha1/ |
| sha1block_arm.s | 31 #define Rd R5 // SHA1 accumulator
83 #define FUNC1(Ra, Rb, Rc, Rd, Re) \
86 AND Rd, Rt1, Rt1 ; \
90 #define FUNC2(Ra, Rb, Rc, Rd, Re) \
92 EOR Rd, Rt1, Rt1
96 #define FUNC3(Ra, Rb, Rc, Rd, Re) \
99 AND Rd, Rt0, Rt0 ; \
107 #define MIX(Ra, Rb, Rc, Rd, Re) \
113 #define ROUND1(Ra, Rb, Rc, Rd, Re) \
115 FUNC1(Ra, Rb, Rc, Rd, Re) ;
[all...] |
| /external/mesa3d/src/mesa/swrast/ |
| s_blend.c | 489 const GLfloat Rd = dest[i][RCOMP];
511 sR = Rd;
516 sR = 1.0F - Rd;
673 dR = Rd;
678 dR = 1.0F - Rd;
743 r = Rs * sR + Rd * dR;
749 r = Rs * sR - Rd * dR;
755 r = Rd * dR - Rs * sR;
761 r = MIN2( Rd, Rs );
766 r = MAX2( Rd, Rs )
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 652 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
657 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
660 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
[all...] |
| /art/disassembler/ |
| disassembler_arm.cc | 278 // Show only Rd and Rm.
291 // Rd is unused (and not shown), and we don't show the 's' suffix either.
560 ArmRegister Rd(instr, 8);
572 args << Rt << "," << Rd << ", [" << Rn;
587 args << Rd << ", " << Rt << ", [" << Rn << ", #" << (imm8 << 2) << "]";
588 if (Rd.r == 13 || Rd.r == 15 || Rt.r == 13 || Rt.r == 15 || Rn.r == 15 ||
589 Rd.r == Rn.r || Rd.r == Rt.r) {
599 Rd = ArmRegister(instr, 0)
[all...] |
| /system/core/libpixelflinger/tests/arch-arm64/assembler/ |
| arm64_assembler_test.cpp | 414 void dataOpTest(dataOpTest_t test, ARMAssemblerInterface *a64asm, uint32_t Rd = 0,
428 regs[Rd] = test.RdValue;
450 case INSTR_ADD: a64asm->ADD(test.cond, test.setFlags, Rd,Rn,op2); break;
451 case INSTR_SUB: a64asm->SUB(test.cond, test.setFlags, Rd,Rn,op2); break;
452 case INSTR_RSB: a64asm->RSB(test.cond, test.setFlags, Rd,Rn,op2); break;
453 case INSTR_AND: a64asm->AND(test.cond, test.setFlags, Rd,Rn,op2); break;
454 case INSTR_ORR: a64asm->ORR(test.cond, test.setFlags, Rd,Rn,op2); break;
455 case INSTR_BIC: a64asm->BIC(test.cond, test.setFlags, Rd,Rn,op2); break;
456 case INSTR_MUL: a64asm->MUL(test.cond, test.setFlags, Rd,Rm,Rs); break;
457 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 116 // Rd = ALLOCA Rs, A
118 // Rd - address of the allocated space
[all...] |
| HexagonInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | [all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-arm.c | 21733 int rd; local
22808 int rd = (newval >> 4) & 0xf; local
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| i386-dis.c | 263 #define Rd { OP_R, d_mode }
[all...] |
