| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyMachineFunctionInfo.cpp | 23 unsigned Reg = UnusedReg;
24 WARegs.resize(MF.getRegInfo().getNumVirtRegs(), Reg);
|
| /external/llvm/lib/CodeGen/ |
| TargetRegisterInfo.cpp | 26 #define DEBUG_TYPE "target-reg-info"
45 Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI,
47 return Printable([Reg, TRI, SubIdx](raw_ostream &OS) {
48 if (!Reg)
50 else if (TargetRegisterInfo::isStackSlot(Reg))
51 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
52 else if (TargetRegisterInfo::isVirtualRegister(Reg))
53 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
54 else if (TRI && Reg < TRI->getNumRegs())
55 OS << '%' << TRI->getName(Reg);
[all...] |
| AllocationOrder.h | 56 unsigned Reg = Order[Pos++];
57 if (!isHint(Reg))
58 return Reg;
|
| DeadMachineInstructionElim.cpp | 75 unsigned Reg = MO.getReg();
76 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
78 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
81 if (!MRI->use_nodbg_empty(Reg))
141 unsigned Reg = MO.getReg();
142 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
146 for (MCSubRegIterator SR(Reg, TRI,/*IncludeSelf=*/true);
160 unsigned Reg = MO.getReg();
161 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
[all...] |
| LivePhysRegs.cpp | 50 unsigned Reg = O->getReg();
51 if (Reg == 0)
53 removeReg(Reg);
62 unsigned Reg = O->getReg();
63 if (Reg == 0)
65 addReg(Reg);
78 unsigned Reg = O->getReg();
79 if (Reg == 0)
84 Clobbers.push_back(std::make_pair(Reg, &*O));
89 removeReg(Reg);
[all...] |
| RegAllocBase.cpp | 75 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
76 if (MRI->reg_nodbg_empty(Reg))
78 enqueue(&LIS->getInterval(Reg));
89 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
92 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
95 LIS->removeInterval(VirtReg->reg);
106 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg))
117 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end();
130 VRM->assignVirt2Phys(VirtReg->reg,
131 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front())
[all...] |
| TargetFrameLoweringImpl.cpp | 80 unsigned Reg = CSRegs[i];
81 if (CallsUnwindInit || MRI.isPhysRegModified(Reg))
82 SavedRegs.set(Reg);
|
| ProcessImplicitDefs.cpp | 79 unsigned Reg = MI->getOperand(0).getReg();
81 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
84 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
108 !TRI->regsOverlap(Reg, UserReg))
110 // UserMI uses or redefines Reg. Set <undef> flags on all uses.
|
| AggressiveAntiDepBreaker.cpp | 60 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
61 unsigned Node = GroupNodeIndices[Reg];
73 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
74 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
75 Regs.push_back(Reg);
82 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
95 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIFixControlFlowLiveIntervals.cpp | 79 unsigned Reg = MI.getOperand(0).getReg();
80 LIS->getInterval(Reg).markNotSpillable();
|
| SILowerI1Copies.cpp | 90 unsigned Reg = MI.getOperand(0).getReg();
91 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
93 MRI.setRegClass(Reg, &AMDGPU::SReg_64RegClass);
148 for (unsigned Reg : I1Defs)
149 MRI.setRegClass(Reg, &AMDGPU::VGPR_32RegClass);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.h | 27 unsigned Reg = 0;
30 Reg = PPC::CR0;
33 Reg = PPC::CR1;
36 Reg = PPC::CR2;
39 Reg = PPC::CR3;
42 Reg = PPC::CR4;
45 Reg = PPC::CR5;
48 Reg = PPC::CR6;
51 Reg = PPC::CR7;
53 assert(Reg != 0 && "Invalid CR bit register")
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameToArgsOffsetElim.cpp | 56 unsigned Reg = OldInst->getOperand(0).getReg();
57 MBBI = TII.loadImmediate(MBB, MBBI, Reg, StackSize);
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCTargetDesc.cpp | 68 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
69 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrInfo.cpp | 121 unsigned Reg = MI->getOperand(0).getReg();
124 MIB = BuildMI(MBB, MI, DL, get(ARM::MOV_ga_pcrel_ldr), Reg)
130 MIB = BuildMI(MBB, MI, DL, get(ARM::LDRi12), Reg);
131 MIB.addReg(Reg, RegState::Kill).addImm(0);
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsELFStreamer.cpp | 31 unsigned Reg = Op.getReg();
32 RegInfoRecord->SetPhysRegUsed(Reg, MCRegInfo);
|
| /art/compiler/debug/dwarf/ |
| register.h | 24 class Reg {
26 explicit Reg(int reg_num) : num_(reg_num) { }
38 static Reg ArmCore(int num) { return Reg(num); } // R0-R15.
39 static Reg ArmFp(int num) { return Reg(64 + num); } // S0?S31.
40 static Reg ArmDp(int num) { return Reg(256 + num); } // D0?D31.
41 static Reg Arm64Core(int num) { return Reg(num); } // X0-X31
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinterDwarf.cpp | 184 int Reg = MRI->getDwarfRegNum(MLoc.getReg(), false);
185 if (Reg < 0) {
190 // probably assert that Reg >= 0 once debug info generation is more
203 Expr.AddRegIndirect(Reg, MLoc.getOffset());
205 Expr.AddReg(Reg);
|
| DwarfExpression.cpp | 90 int Reg = TRI.getDwarfRegNum(MachineReg, false);
93 if (Reg >= 0) {
94 AddReg(Reg);
103 Reg = TRI.getDwarfRegNum(*SR, false);
104 if (Reg >= 0) {
108 AddReg(Reg, "super-register");
139 Reg = TRI.getDwarfRegNum(*SR, false);
149 if (Reg >= 0 && Intersection.any()) {
150 AddReg(Reg, "sub-register");
|
| /external/llvm/lib/Target/NVPTX/InstPrinter/ |
| NVPTXInstPrinter.cpp | 82 unsigned Reg = Op.getReg();
83 printRegName(O, Reg);
|
| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcMCTargetDesc.cpp | 39 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
40 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
48 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
49 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047);
|
| /prebuilts/python/darwin-x86/2.7.5/lib/python2.7/distutils/tests/ |
| test_msvc9compiler.py | 124 from distutils.msvc9compiler import Reg
125 self.assertRaises(KeyError, Reg.get_value, 'xxx', 'xxx')
130 v = Reg.get_value(path, u'dragfullwindows')
135 keys = Reg.read_keys(HKCU, 'xxxx')
138 keys = Reg.read_keys(HKCU, r'Control Panel')
|
| /prebuilts/python/linux-x86/2.7.5/lib/python2.7/distutils/tests/ |
| test_msvc9compiler.py | 124 from distutils.msvc9compiler import Reg
125 self.assertRaises(KeyError, Reg.get_value, 'xxx', 'xxx')
130 v = Reg.get_value(path, u'dragfullwindows')
135 keys = Reg.read_keys(HKCU, 'xxxx')
138 keys = Reg.read_keys(HKCU, r'Control Panel')
|
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| DynamicTypeChecker.cpp | 44 DynamicTypeBugVisitor(const MemRegion *Reg) : Reg(Reg) {}
49 ID.AddPointer(Reg);
59 const MemRegion *Reg;
63 const MemRegion *Reg, const Stmt *ReportedNode,
73 const MemRegion *Reg,
88 R->markInteresting(Reg);
89 R->addVisitor(llvm::make_unique<DynamicTypeBugVisitor>(Reg));
100 DynamicTypeInfo TrackedType = getDynamicTypeInfo(State, Reg);
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 66 OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
269 // a single GPRPair reg operand is used in the .td file to replace the two
279 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
280 if (MRC.contains(Reg)) {
288 Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID)));
323 unsigned Reg = Op.getReg();
324 printRegName(O, Reg);
386 // REG 0 0 - e.g. R5
387 // REG REG 0,SH_OPC - e.g. R5, ROR R
[all...] |
