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Searched
defs:RegIndex
(Results
1 - 4
of
4
) sorted by null
/external/llvm/lib/Target/AMDGPU/
AMDGPUInstrInfo.cpp
121
unsigned
RegIndex
= MI->getOperand(RegOpIdx).getImm();
123
unsigned Address = calculateIndirectAddress(
RegIndex
, Channel);
135
unsigned
RegIndex
= MI->getOperand(RegOpIdx).getImm();
137
unsigned Address = calculateIndirectAddress(
RegIndex
, Channel);
144
calculateIndirectAddress(
RegIndex
, Channel),
286
unsigned
RegIndex
;
288
for (
RegIndex
= 0, RegEnd = IndirectRC->getNumRegs();
RegIndex
!= RegEnd;
289
++
RegIndex
) {
290
if (IndirectRC->getRegister(
RegIndex
) == Reg
[
all
...]
R600ISelLowering.cpp
619
int64_t
RegIndex
= cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
620
unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(
RegIndex
);
653
int64_t
RegIndex
= cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
654
unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(
RegIndex
);
[
all
...]
/external/mesa3d/src/gallium/drivers/radeon/
R600ISelLowering.cpp
99
int64_t
RegIndex
= MI->getOperand(1).getImm();
100
unsigned ConstantReg = AMDGPU::R600_CReg32RegClass.getRegister(
RegIndex
);
261
int64_t
RegIndex
= cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
262
unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(
RegIndex
);
282
int64_t
RegIndex
= cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
283
unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(
RegIndex
);
/external/llvm/lib/CodeGen/
RegisterCoalescer.cpp
[
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...]
Completed in 238 milliseconds