/external/llvm/lib/Target/X86/ |
X86MachineFunctionInfo.cpp | 20 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( 22 unsigned SlotSize = RegInfo->getSlotSize(); 24 RegInfo->X86RegisterInfo::getCalleeSavedRegs(MF);
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X86CallFrameOptimization.cpp | 100 const X86RegisterInfo &RegInfo, 257 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) { 298 if (!RegInfo.isPhysicalRegister(Reg)) 300 if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister())) 304 if (RegInfo.regsOverlap(Reg, U)) 318 const X86RegisterInfo &RegInfo = *static_cast<const X86RegisterInfo *>( 363 while ((Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs)) != 409 if (RegInfo.isPhysicalRegister(Reg))
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/external/llvm/lib/Target/NVPTX/ |
NVPTXInstrInfo.h | 27 const NVPTXRegisterInfo RegInfo; 32 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
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NVPTXPrologEpilogPass.cpp | 113 const TargetRegisterInfo *RegInfo = Fn.getSubtarget().getRegisterInfo(); 213 (RegInfo->needsStackRealignment(Fn) && MFI->getObjectIndexEnd() != 0))
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/external/llvm/lib/Target/AArch64/ |
AArch64CleanupLocalDynamicTLSPass.cpp | 116 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 117 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass);
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/external/llvm/lib/Target/ARM/ |
ARMISelLowering.h | 481 const TargetRegisterInfo *RegInfo;
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Thumb1FrameLowering.cpp | 57 const ThumbRegisterInfo *RegInfo = 76 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); 79 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); 93 const ThumbRegisterInfo *RegInfo = 108 unsigned FramePtr = RegInfo->getFrameRegister(MF); 109 unsigned BasePtr = RegInfo->getBaseRegister(); 122 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, 134 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize), 267 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, 289 if (RegInfo->needsStackRealignment(MF) [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZLDCleanup.cpp | 132 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 133 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&SystemZ::GR64BitRegClass);
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/external/llvm/lib/Target/WebAssembly/ |
WebAssemblyFrameLowering.cpp | 47 const auto *RegInfo = 51 RegInfo->needsStackRealignment(MF);
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/external/llvm/lib/Target/Mips/ |
MipsSERegisterInfo.cpp | 116 const MipsRegisterInfo *RegInfo = 143 else if (RegInfo->needsStackRealignment(MF)) { 184 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); 185 unsigned Reg = RegInfo.createVirtualRegister(PtrRC);
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Mips16ISelDAGToDAG.cpp | 74 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 80 V0 = RegInfo.createVirtualRegister(RC); 81 V1 = RegInfo.createVirtualRegister(RC); 82 V2 = RegInfo.createVirtualRegister(RC);
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MipsSEInstrInfo.cpp | 454 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); 471 unsigned Reg = RegInfo.createVirtualRegister(RC);
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/external/llvm/lib/Target/Sparc/ |
SparcFrameLowering.cpp | 93 const SparcRegisterInfo &RegInfo = 99 bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF); 158 unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true); 171 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true); 172 unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true); 234 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); 238 RegInfo->needsStackRealignment(MF) || 248 const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); 266 } else if (RegInfo->needsStackRealignment(MF)) { 280 FrameReg = RegInfo->getFrameRegister(MF) [all...] |
SparcInstrInfo.cpp | 456 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 460 GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
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/external/llvm/include/llvm/CodeGen/ |
FunctionLoweringInfo.h | 59 MachineRegisterInfo *RegInfo;
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MachineFunction.h | 95 // RegInfo - Information about each register in use in the function. 96 MachineRegisterInfo *RegInfo; 202 MachineRegisterInfo &getRegInfo() { return *RegInfo; } 203 const MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
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SelectionDAGISel.h | 48 MachineRegisterInfo *RegInfo;
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/external/llvm/lib/CodeGen/ |
GCRootLowering.cpp | 343 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); 345 RegInfo->needsStackRealignment(MF);
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StackMaps.cpp | 337 const TargetRegisterInfo *RegInfo = AP.MF->getSubtarget().getRegisterInfo(); 339 MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(*(AP.MF));
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MachineFunction.cpp | 68 RegInfo = new (Allocator) MachineRegisterInfo(this); 70 RegInfo = nullptr; 116 if (RegInfo) { 117 RegInfo->~MachineRegisterInfo(); 118 Allocator.Deallocate(RegInfo); 365 if (RegInfo) { 366 OS << (RegInfo->isSSA() ? "SSA" : "Post SSA"); 367 if (!RegInfo->tracksLiveness()) 384 if (RegInfo && !RegInfo->livein_empty()) [all...] |
PrologEpilogInserter.cpp | 302 const TargetRegisterInfo *RegInfo = F.getSubtarget().getRegisterInfo(); 303 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&F); 314 if (!TFI->assignCalleeSavedSpillSlots(F, RegInfo, CSI)) { 329 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); 332 if (RegInfo->hasReservedSpillSlot(F, Reg, FrameIdx)) { 620 const TargetRegisterInfo *RegInfo = Fn.getSubtarget().getRegisterInfo(); 623 RegInfo->useFPForScavengingIndex(Fn) && 624 !RegInfo->needsStackRealignment(Fn)); 752 (RegInfo->needsStackRealignment(Fn) && MFI->getObjectIndexEnd() != 0)) [all...] |
/external/llvm/lib/CodeGen/MIRParser/ |
MIRParser.cpp | 338 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 339 assert(RegInfo.isSSA()); 341 RegInfo.leaveSSA(); 342 assert(RegInfo.tracksLiveness()); 344 RegInfo.invalidateLiveness(); 345 RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness); 355 unsigned Reg = RegInfo.createVirtualRegister(RC); 367 RegInfo.setSimpleHint(Reg, PreferredReg); 383 RegInfo.addLiveIn(Reg, VReg); 387 BitVector CalleeSavedRegisterMask(RegInfo.getUsedPhysRegsMask().size()) [all...] |
/external/llvm/lib/Target/XCore/Disassembler/ |
XCoreDisassembler.cpp | 72 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 73 return *(RegInfo->getRegClass(RC).begin() + RegNo);
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/external/llvm/lib/Target/BPF/ |
BPFISelLowering.cpp | 201 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 219 unsigned VReg = RegInfo.createVirtualRegister(&BPF::GPRRegClass); 220 RegInfo.addLiveIn(VA.getLocReg(), VReg);
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/external/llvm/include/llvm/Target/ |
TargetInstrInfo.h | [all...] |