/prebuilts/go/darwin-x86/src/crypto/rc4/ |
rc4_arm.s | 12 #define Rn R2 26 MOVW n+8(FP), Rn 56 CMP Rk, Rn
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/prebuilts/go/linux-x86/src/crypto/rc4/ |
rc4_arm.s | 12 #define Rn R2 26 MOVW n+8(FP), Rn 56 CMP Rk, Rn
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/external/llvm/lib/Target/AArch64/Disassembler/ |
AArch64Disassembler.cpp | 653 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 658 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 661 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMMCCodeEmitter.cpp | [all...] |
/external/v8/src/arm/ |
disasm-arm.cc | 91 void FormatNeonMemory(int Rn, int align, int Rm); 303 if (format[1] == 'n') { // 'rn: Rn register 416 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) { 418 "[r%d", Rn); 732 // Rn field to encode it. 733 Format(instr, "mul'cond's 'rn, 'rm, 'rs"); 737 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the 738 // Rn field to encode the Rd register and the Rd field to encode 739 // the Rn register [all...] |
simulator-arm.cc | 750 FPSCR_rounding_mode_ = RN; 2128 int rn = instr->RnValue(); local 2205 int rn = instr->RnValue(); local 2401 int rn = instr->RnValue(); local 2631 int rn = instr->RnValue(); local 2695 int rn = instr->RnValue(); local 3722 int rn = instr->RnValue(); local 3759 int rn = instr->RnValue(); local 3776 int rn = instr->RnValue(); local [all...] |
/toolchain/binutils/binutils-2.25/include/opcode/ |
tic30.h | 190 #define Rn 0x0001 209 #define GAddr1 Rn | Direct | Indirect | Imm16 211 #define TAddr1 op3T1 | Rn | Indirect 212 #define TAddr2 op3T2 | Rn | Indirect 213 #define Reg Rn | ARn 247 { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, 251 { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, 252 { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, 347 { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, 408 { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt } [all...] |
/art/disassembler/ |
disassembler_arm.cc | 315 ArmRegister rn(instruction, 16); 316 if (rn.r == 0xf) { 322 args << "[" << rn << ", #" << offset << "]"; 324 args << "[" << rn << ", #" << offset << "]!"; 326 args << "[" << rn << "], #" << offset; 330 if (rn.r == 9) { 516 // |111|01|00|op|0|WL| Rn | | 525 ArmRegister Rn(instr, 16); 530 args << Rn << (W == 0 ? "" : "!") << ", "; 532 if (Rn.r != 13) [all...] |
/system/core/libpixelflinger/tests/arch-arm64/assembler/ |
arm64_assembler_test.cpp | 415 uint32_t Rn = 1, uint32_t Rm = 2, uint32_t Rs = 3) 429 regs[Rn] = test.RnValue; 450 case INSTR_ADD: a64asm->ADD(test.cond, test.setFlags, Rd,Rn,op2); break; 451 case INSTR_SUB: a64asm->SUB(test.cond, test.setFlags, Rd,Rn,op2); break; 452 case INSTR_RSB: a64asm->RSB(test.cond, test.setFlags, Rd,Rn,op2); break; 453 case INSTR_AND: a64asm->AND(test.cond, test.setFlags, Rd,Rn,op2); break; 454 case INSTR_ORR: a64asm->ORR(test.cond, test.setFlags, Rd,Rn,op2); break; 455 case INSTR_BIC: a64asm->BIC(test.cond, test.setFlags, Rd,Rn,op2); break; 457 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break; 458 case INSTR_CMP: a64asm->CMP(test.cond, Rn,op2); break [all...] |
/toolchain/binutils/binutils-2.25/opcodes/ |
arm-dis.c | 2015 int rn = (given >> 16) & 0xf; local 2441 const char *rn = arm_regnames [(given >> 16) & 0xf]; local 2668 int rn = ((given >> 16) & 0xf); local 2698 int rn = ((given >> 16) & 0xf); local 2773 int rn = ((given >> 16) & 0xf); local [all...] |
/external/llvm/lib/Target/ARM/ |
ARMBaseInstrInfo.cpp | [all...] |
/external/llvm/lib/Target/ARM/Disassembler/ |
ARMDisassembler.cpp | [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
AArch64AsmParser.cpp | [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
ARMAsmParser.cpp | [all...] |
/toolchain/binutils/binutils-2.25/gas/config/ |
tc-arm.c | [all...] |