/external/valgrind/none/tests/mips64/ |
shift_instructions.c | 10 SRA, SRAV, SRL, SRLV 177 case SRA: 178 TEST2("sra $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1); 179 TEST2("sra $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3); 180 TEST2("sra $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1); 181 TEST2("sra $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
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/external/llvm/include/llvm/TableGen/ |
Record.h | 727 enum BinaryOp { ADD, AND, SHL, SRA, SRL, LISTCONCAT, STRCONCAT, CONCAT, EQ }; [all...] |
/external/llvm/lib/Target/AMDGPU/ |
R600ISelLowering.cpp | [all...] |
/external/pcre/dist/sljit/ |
sljitNativeMIPS_common.c | 169 #define SRA (HI(0) | LO(3)) [all...] |
sljitNativeSPARC_common.c | 152 #define SRA (OPC1(0x2) | OPC3(0x27)) 789 FAIL_IF(push_inst(compiler, SRA | D(TMP_REG1) | S1(SLJIT_R0) | IMM(31), DR(TMP_REG1))); [all...] |
/system/core/libpixelflinger/codeflinger/ |
MIPSAssembler.cpp | 399 case ASR: mMips->SRA(tmpReg, amode.reg, amode.value); break; 510 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break; 542 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break; [all...] |
/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 336 SHL, SRA, SRL, ROTL, ROTR, 405 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
DAGCombiner.cpp | [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.cpp | 667 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom); [all...] |
/external/v8/src/s390/ |
constants-s390.h | [all...] |