| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | 266 EVT SVT = VT;
267 while (SVT != MVT::f32 && SVT != MVT::f16) {
268 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
269 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
272 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
274 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
276 VT = SVT;
[all...] |
| LegalizeFloatTypes.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 211 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
216 if (!TLI.isTypeLegal(SVT))
217 SVT = NVT;
219 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
590 EVT SVT = getSetCCResultType(N->getOperand(0).getValueType());
596 if (!TLI.isTypeLegal(SVT))
597 SVT = NVT;
600 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
615 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
618 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?")
[all...] |
| LegalizeVectorTypes.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 337 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
349 switch (SVT) {
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCalls.cpp | 279 auto SVT = VT->getElementType();
281 unsigned BitWidth = SVT->getPrimitiveSizeInBits();
298 auto ShiftAmt = ConstantInt::get(SVT, Count.zextOrTrunc(BitWidth));
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
