/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeDAG.cpp | 412 SDValue ShiftAmount = 416 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 580 SDValue ShiftAmount = 583 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); [all...] |
LegalizeVectorOps.cpp | 845 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT); 847 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), 848 ShiftAmount); [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 758 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 765 if (Opc == ISD::SRL && ShiftAmount) { 769 ShiftAmount -= 1; 772 while (ShiftAmount--) [all...] |
/external/llvm/lib/Analysis/ |
InstructionSimplify.cpp | [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
InstCombineCasts.cpp | 457 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; 459 if ((VecWidth % DestWidth != 0) || (ShiftAmount % DestWidth != 0)) 470 unsigned Elt = ShiftAmount / DestWidth; [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
AArch64AsmParser.cpp | 197 unsigned ShiftAmount; 349 return ShiftedImm.ShiftAmount; 702 unsigned Shift = ShiftedImm.ShiftAmount; 740 unsigned Shift = ShiftedImm.ShiftAmount; [all...] |
/external/llvm/lib/Target/Mips/AsmParser/ |
MipsAsmParser.cpp | [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.cpp | [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
ARMAsmParser.cpp | 205 unsigned &ShiftAmount); [all...] |