| /external/llvm/lib/Target/Hexagon/ |
| HexagonOptimizeSZextends.cpp | 103 // %sext233 = shl i32 %34, 16
118 Instruction *Shl = dyn_cast<Instruction>(Ashr->getOperand(0));
119 if (!(Shl && Shl->getOpcode() == Instruction::Shl))
121 Value *Intr = Shl->getOperand(0);
122 Value *ShlOp1 = Shl->getOperand(1);
128 // The first operand of Shl comes from an intrinsic.
|
| /external/llvm/unittests/ADT/ |
| APIntTest.cpp | 30 APInt Shl = One.shl(0);
31 EXPECT_TRUE(Shl[0]);
32 EXPECT_FALSE(Shl[1]);
164 EXPECT_EQ(zero, one.shl(1));
165 EXPECT_EQ(one, one.shl(0));
462 testDiv(APInt{4096, 5}.shl(2001),
463 APInt{4096, 1}.shl(2000),
469 testDiv(APInt{1024, 19}.shl(811),
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCExpr.h | 428 Shl, ///< Shift left.
506 return create(Shl, LHS, RHS, Ctx);
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 65 if (I->getOpcode() == Instruction::Shl && !I->hasNoUnsignedWrap()) {
205 Constant *Shl = ConstantExpr::getShl(C1, C2);
207 BinaryOperator *BO = BinaryOperator::CreateMul(NewOp, Shl);
211 Shl->isNotMinSignedValue())
228 BinaryOperator *Shl = BinaryOperator::CreateShl(NewOp, NewCst);
231 Shl->setHasNoUnsignedWrap();
235 Shl->setHasNoSignedWrap();
238 return Shl;
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelDAGToDAG.cpp | [all...] |
| AMDGPUISelLowering.cpp | 303 setOperationAction(ISD::SHL, VT, Expand);
372 setTargetDAGCombine(ISD::SHL);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/llvm/bindings/ocaml/llvm/ |
| llvm.ml | 173 | Shl
[all...] |
| /external/v8/src/crankshaft/ |
| hydrogen-instructions.cc | 244 void Range::Shl(int32_t value) {
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
