| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.h | 42 unsigned SrcIdx;
61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
109 unsigned getSrcIdx() const { return SrcIdx; }
|
| PeepholeOptimizer.cpp | [all...] |
| TwoAddressInstructionPass.cpp | 132 unsigned SrcIdx, unsigned DstIdx,
[all...] |
| RegisterCoalescer.cpp | 305 SrcIdx = DstIdx = 0;
352 SrcIdx, DstIdx);
357 SrcIdx = DstSub;
374 if (DstIdx && !SrcIdx) {
376 std::swap(SrcIdx, DstIdx);
395 std::swap(SrcIdx, DstIdx);
419 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
433 return TRI.composeSubRegIndices(SrcIdx, SrcSub) ==
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600InstrInfo.cpp | 269 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const {
285 if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) {
330 int SrcIdx = getOperandIdx(MI->getOpcode(), OpTable[j][0]);
331 if (SrcIdx < 0)
333 MachineOperand &MO = MI->getOperand(SrcIdx);
334 unsigned Reg = MI->getOperand(SrcIdx).getReg();
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineVectorOps.cpp | 213 int SrcIdx = SVI->getMaskValue(Elt->getZExtValue());
218 if (SrcIdx < 0)
220 if (SrcIdx < (int)LHSWidth)
223 SrcIdx -= LHSWidth;
229 SrcIdx, false));
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
