| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 47 /// number in the SrcVT type is expanded to fill the src xmm register and the
49 static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) {
58 SrcVT = MVT::v16i8;
63 SrcVT = MVT::v16i8;
70 SrcVT = MVT::v16i8;
75 SrcVT = MVT::v16i8;
82 SrcVT = MVT::v16i8;
87 SrcVT = MVT::v16i8;
95 SrcVT = MVT::v8i16;
100 SrcVT = MVT::v8i16
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86SelectionDAGInfo.cpp | 268 EVT SrcVT = Src.getValueType();
274 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
276 SrcVT)),
|
| X86ISelDAGToDAG.cpp | 595 MVT SrcVT = N->getOperand(0).getSimpleValueType();
599 if (SrcVT.isVector() || DstVT.isVector())
606 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
627 MemVT = SrcIsSSE ? SrcVT : DstVT;
[all...] |
| X86FastISel.cpp | 96 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
567 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
570 unsigned Src, EVT SrcVT,
572 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Scalarizer.cpp | 489 VectorType *SrcVT = dyn_cast<VectorType>(BCI.getSrcTy());
490 if (!DstVT || !SrcVT)
494 unsigned SrcNumElems = SrcVT->getNumElements();
526 Type *MidTy = VectorType::get(SrcVT->getElementType(), FanIn);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 499 EVT SrcVT = LD->getMemoryVT();
504 unsigned NumElem = SrcVT.getVectorNumElements();
506 EVT SrcEltVT = SrcVT.getScalarType();
509 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
525 unsigned RemainingBytes = SrcVT.getStoreSize();
617 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
623 SrcVT.getScalarType(),
812 EVT SrcVT = Src.getValueType();
813 int NumSrcElements = SrcVT.getVectorNumElements();
827 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask))
[all...] |
| FastISel.cpp | [all...] |
| LegalizeFloatTypes.cpp | [all...] |
| SelectionDAGISel.cpp | 699 EVT SrcVT = Src.getValueType();
700 if (!SrcVT.isInteger() || SrcVT.isVector())
[all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| LegalizeVectorTypes.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 368 EVT SrcVT;
370 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT();
372 SrcVT = N.getOperand(0).getValueType();
374 if (!IsLoadStore && SrcVT == MVT::i8)
376 else if (!IsLoadStore && SrcVT == MVT::i16)
378 else if (SrcVT == MVT::i32)
380 assert(SrcVT != MVT::i64 && "extend from 64-bits?");
385 EVT SrcVT = N.getOperand(0).getValueType();
386 if (!IsLoadStore && SrcVT == MVT::i8)
388 else if (!IsLoadStore && SrcVT == MVT::i16
[all...] |
| AArch64FastISel.cpp | 154 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
189 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
220 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
224 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
228 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
[all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelDAGToDAG.cpp | [all...] |
| SIISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 126 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
127 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
130 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
132 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
133 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
135 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
939 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
942 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
1013 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1016 if (SrcVT != MVT::f64 || DestVT != MVT::f32
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 163 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
806 MVT SrcVT = SrcEVT.getSimpleVT();
808 if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits())
821 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
822 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
832 switch (SrcVT.SimpleTy) {
872 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 181 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| CodeGenPrepare.cpp | 775 EVT SrcVT = TLI.getValueType(DL, CI->getOperand(0)->getType());
779 if (SrcVT.isInteger() != DstVT.isInteger())
784 if (SrcVT.bitsLT(DstVT)) return false;
789 if (TLI.getTypeAction(CI->getContext(), SrcVT) ==
791 SrcVT = TLI.getTypeToTransformTo(CI->getContext(), SrcVT);
797 if (SrcVT != DstVT)
[all...] |
