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    Searched defs:TSFlags (Results 1 - 9 of 9) sorted by null

  /external/llvm/lib/Target/NVPTX/
NVPTXInstrInfo.cpp 69 // Look for the appropriate part of TSFlags
72 unsigned TSFlags =
73 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift;
74 isMove = (TSFlags == 1);
93 unsigned TSFlags =
94 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift;
95 isLoad = (TSFlags == 1);
104 unsigned TSFlags =
105 (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift;
106 isStore = (TSFlags == 1)
    [all...]
  /external/llvm/lib/Target/X86/InstPrinter/
X86ATTInstPrinter.cpp 43 uint64_t TSFlags = Desc.TSFlags;
50 if (TSFlags & X86II::LOCK)
X86IntelInstPrinter.cpp 39 uint64_t TSFlags = Desc.TSFlags;
41 if (TSFlags & X86II::LOCK)
  /external/llvm/lib/Target/PowerPC/
PPCHazardRecognizers.cpp 287 uint64_t TSFlags = MCID.TSFlags;
289 isFirst = TSFlags & PPCII::PPC970_First;
290 isSingle = TSFlags & PPCII::PPC970_Single;
291 isCracked = TSFlags & PPCII::PPC970_Cracked;
292 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
  /external/llvm/lib/Target/AMDGPU/
SIInsertWaits.cpp 146 uint64_t TSFlags = MI.getDesc().TSFlags;
149 Result.Named.VM = !!(TSFlags & SIInstrFlags::VM_CNT);
152 Result.Named.EXP = !!(TSFlags & SIInstrFlags::EXP_CNT &&
156 if (TSFlags & SIInstrFlags::LGKM_CNT) {
  /external/llvm/lib/Target/X86/MCTargetDesc/
X86MCCodeEmitter.cpp 148 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
156 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
163 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
185 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
186 assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) &&
190 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift;
209 /// in an instruction with the specified TSFlags.
210 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
211 unsigned Size = X86II::getSizeOfImm(TSFlags);
212 bool isPCRel = X86II::isImmPCRel(TSFlags);
    [all...]
  /external/llvm/include/llvm/MC/
MCInstrDesc.h 146 uint64_t TSFlags; // Target Specific Flag values
  /external/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 597 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
599 if ((getForcedEncodingSize() == 32 && (TSFlags & SIInstrFlags::VOP3)) ||
600 (getForcedEncodingSize() == 64 && !(TSFlags & SIInstrFlags::VOP3)))
603 if ((TSFlags & SIInstrFlags::VOP3) &&
604 (TSFlags & SIInstrFlags::VOPAsmPrefer32Bit) &&
    [all...]
  /external/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp 138 uint64_t TSFlags = MI->getDesc().TSFlags;
140 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
157 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
572 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
    [all...]

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