1 /* Print mips instructions for GDB, the GNU debugger, or for objdump. 2 Copyright (C) 1989-2014 Free Software Foundation, Inc. 3 Contributed by Nobuyuki Hikichi(hikichi (at) sra.co.jp). 4 5 This file is part of the GNU opcodes library. 6 7 This library is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 It is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 20 MA 02110-1301, USA. */ 21 22 #include "sysdep.h" 23 #include "dis-asm.h" 24 #include "libiberty.h" 25 #include "opcode/mips.h" 26 #include "opintl.h" 27 28 /* FIXME: These are needed to figure out if the code is mips16 or 29 not. The low bit of the address is often a good indicator. No 30 symbol table is available when this code runs out in an embedded 31 system as when it is used for disassembler support in a monitor. */ 32 33 #if !defined(EMBEDDED_ENV) 34 #define SYMTAB_AVAILABLE 1 35 #include "elf-bfd.h" 36 #include "elf/mips.h" 37 #endif 38 39 /* Mips instructions are at maximum this many bytes long. */ 40 #define INSNLEN 4 41 42 43 /* FIXME: These should be shared with gdb somehow. */ 45 46 struct mips_cp0sel_name 47 { 48 unsigned int cp0reg; 49 unsigned int sel; 50 const char * const name; 51 }; 52 53 static const char * const mips_gpr_names_numeric[32] = 54 { 55 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 56 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 57 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 58 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 59 }; 60 61 static const char * const mips_gpr_names_oldabi[32] = 62 { 63 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 64 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 65 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 66 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 67 }; 68 69 static const char * const mips_gpr_names_newabi[32] = 70 { 71 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 72 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 73 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 74 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 75 }; 76 77 static const char * const mips_gpr_names_xr[17] = { 78 "xr0", "xr1", "xr2", "xr3", "xr4", "xr5", "xr6", "xr7", 79 "xr8", "xr9", "xr10", "xr11", "xr12", "xr13", "xr14", "xr15", 80 "xr16" 81 }; 82 83 static const char * const mips_fpr_names_numeric[32] = 84 { 85 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 86 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 87 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 88 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" 89 }; 90 91 static const char * const mips_fpr_names_32[32] = 92 { 93 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", 94 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", 95 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", 96 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" 97 }; 98 99 static const char * const mips_fpr_names_n32[32] = 100 { 101 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", 102 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 103 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", 104 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" 105 }; 106 107 static const char * const mips_fpr_names_64[32] = 108 { 109 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", 110 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 111 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", 112 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" 113 }; 114 115 static const char * const mips_cp0_names_numeric[32] = 116 { 117 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 118 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 119 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 120 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 121 }; 122 123 static const char * const mips_cp1_names_numeric[32] = 124 { 125 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 126 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 127 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 128 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 129 }; 130 131 static const char * const mips_cp0_names_r3000[32] = 132 { 133 "c0_index", "c0_random", "c0_entrylo", "$3", 134 "c0_context", "$5", "$6", "$7", 135 "c0_badvaddr", "$9", "c0_entryhi", "$11", 136 "c0_sr", "c0_cause", "c0_epc", "c0_prid", 137 "$16", "$17", "$18", "$19", 138 "$20", "$21", "$22", "$23", 139 "$24", "$25", "$26", "$27", 140 "$28", "$29", "$30", "$31", 141 }; 142 143 static const char * const mips_cp0_names_r4000[32] = 144 { 145 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 146 "c0_context", "c0_pagemask", "c0_wired", "$7", 147 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 148 "c0_sr", "c0_cause", "c0_epc", "c0_prid", 149 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 150 "c0_xcontext", "$21", "$22", "$23", 151 "$24", "$25", "c0_ecc", "c0_cacheerr", 152 "c0_taglo", "c0_taghi", "c0_errorepc", "$31", 153 }; 154 155 static const char * const mips_cp0_names_r5900[32] = 156 { 157 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 158 "c0_context", "c0_pagemask", "c0_wired", "$7", 159 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 160 "c0_sr", "c0_cause", "c0_epc", "c0_prid", 161 "c0_config", "$17", "$18", "$19", 162 "$20", "$21", "$22", "c0_badpaddr", 163 "c0_depc", "c0_perfcnt", "$26", "$27", 164 "c0_taglo", "c0_taghi", "c0_errorepc", "$31" 165 }; 166 167 static const struct mips_cp0sel_name mips_cp0sel_names_mipsr5900[] = 168 { 169 { 24, 2, "c0_iab" }, 170 { 24, 3, "c0_iabm" }, 171 { 24, 4, "c0_dab" }, 172 { 24, 5, "c0_dabm" }, 173 { 24, 6, "c0_dvb" }, 174 { 24, 7, "c0_dvbm" }, 175 { 25, 1, "c0_perfcnt,1" }, 176 { 25, 2, "c0_perfcnt,2" } 177 }; 178 179 static const char * const mips_cp0_names_mips3264[32] = 180 { 181 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 182 "c0_context", "c0_pagemask", "c0_wired", "$7", 183 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 184 "c0_status", "c0_cause", "c0_epc", "c0_prid", 185 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 186 "c0_xcontext", "$21", "$22", "c0_debug", 187 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 188 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 189 }; 190 191 static const char * const mips_cp1_names_mips3264[32] = 192 { 193 "c1_fir", "c1_ufr", "$2", "$3", 194 "c1_unfr", "$5", "$6", "$7", 195 "$8", "$9", "$10", "$11", 196 "$12", "$13", "$14", "$15", 197 "$16", "$17", "$18", "$19", 198 "$20", "$21", "$22", "$23", 199 "$24", "c1_fccr", "c1_fexr", "$27", 200 "c1_fenr", "$29", "$30", "c1_fcsr" 201 }; 202 203 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = 204 { 205 { 16, 1, "c0_config1" }, 206 { 16, 2, "c0_config2" }, 207 { 16, 3, "c0_config3" }, 208 { 18, 1, "c0_watchlo,1" }, 209 { 18, 2, "c0_watchlo,2" }, 210 { 18, 3, "c0_watchlo,3" }, 211 { 18, 4, "c0_watchlo,4" }, 212 { 18, 5, "c0_watchlo,5" }, 213 { 18, 6, "c0_watchlo,6" }, 214 { 18, 7, "c0_watchlo,7" }, 215 { 19, 1, "c0_watchhi,1" }, 216 { 19, 2, "c0_watchhi,2" }, 217 { 19, 3, "c0_watchhi,3" }, 218 { 19, 4, "c0_watchhi,4" }, 219 { 19, 5, "c0_watchhi,5" }, 220 { 19, 6, "c0_watchhi,6" }, 221 { 19, 7, "c0_watchhi,7" }, 222 { 25, 1, "c0_perfcnt,1" }, 223 { 25, 2, "c0_perfcnt,2" }, 224 { 25, 3, "c0_perfcnt,3" }, 225 { 25, 4, "c0_perfcnt,4" }, 226 { 25, 5, "c0_perfcnt,5" }, 227 { 25, 6, "c0_perfcnt,6" }, 228 { 25, 7, "c0_perfcnt,7" }, 229 { 27, 1, "c0_cacheerr,1" }, 230 { 27, 2, "c0_cacheerr,2" }, 231 { 27, 3, "c0_cacheerr,3" }, 232 { 28, 1, "c0_datalo" }, 233 { 29, 1, "c0_datahi" } 234 }; 235 236 static const char * const mips_cp0_names_mips3264r2[32] = 237 { 238 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 239 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", 240 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 241 "c0_status", "c0_cause", "c0_epc", "c0_prid", 242 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 243 "c0_xcontext", "$21", "$22", "c0_debug", 244 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 245 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 246 }; 247 248 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = 249 { 250 { 4, 1, "c0_contextconfig" }, 251 { 0, 1, "c0_mvpcontrol" }, 252 { 0, 2, "c0_mvpconf0" }, 253 { 0, 3, "c0_mvpconf1" }, 254 { 1, 1, "c0_vpecontrol" }, 255 { 1, 2, "c0_vpeconf0" }, 256 { 1, 3, "c0_vpeconf1" }, 257 { 1, 4, "c0_yqmask" }, 258 { 1, 5, "c0_vpeschedule" }, 259 { 1, 6, "c0_vpeschefback" }, 260 { 2, 1, "c0_tcstatus" }, 261 { 2, 2, "c0_tcbind" }, 262 { 2, 3, "c0_tcrestart" }, 263 { 2, 4, "c0_tchalt" }, 264 { 2, 5, "c0_tccontext" }, 265 { 2, 6, "c0_tcschedule" }, 266 { 2, 7, "c0_tcschefback" }, 267 { 5, 1, "c0_pagegrain" }, 268 { 6, 1, "c0_srsconf0" }, 269 { 6, 2, "c0_srsconf1" }, 270 { 6, 3, "c0_srsconf2" }, 271 { 6, 4, "c0_srsconf3" }, 272 { 6, 5, "c0_srsconf4" }, 273 { 12, 1, "c0_intctl" }, 274 { 12, 2, "c0_srsctl" }, 275 { 12, 3, "c0_srsmap" }, 276 { 15, 1, "c0_ebase" }, 277 { 16, 1, "c0_config1" }, 278 { 16, 2, "c0_config2" }, 279 { 16, 3, "c0_config3" }, 280 { 18, 1, "c0_watchlo,1" }, 281 { 18, 2, "c0_watchlo,2" }, 282 { 18, 3, "c0_watchlo,3" }, 283 { 18, 4, "c0_watchlo,4" }, 284 { 18, 5, "c0_watchlo,5" }, 285 { 18, 6, "c0_watchlo,6" }, 286 { 18, 7, "c0_watchlo,7" }, 287 { 19, 1, "c0_watchhi,1" }, 288 { 19, 2, "c0_watchhi,2" }, 289 { 19, 3, "c0_watchhi,3" }, 290 { 19, 4, "c0_watchhi,4" }, 291 { 19, 5, "c0_watchhi,5" }, 292 { 19, 6, "c0_watchhi,6" }, 293 { 19, 7, "c0_watchhi,7" }, 294 { 23, 1, "c0_tracecontrol" }, 295 { 23, 2, "c0_tracecontrol2" }, 296 { 23, 3, "c0_usertracedata" }, 297 { 23, 4, "c0_tracebpc" }, 298 { 25, 1, "c0_perfcnt,1" }, 299 { 25, 2, "c0_perfcnt,2" }, 300 { 25, 3, "c0_perfcnt,3" }, 301 { 25, 4, "c0_perfcnt,4" }, 302 { 25, 5, "c0_perfcnt,5" }, 303 { 25, 6, "c0_perfcnt,6" }, 304 { 25, 7, "c0_perfcnt,7" }, 305 { 27, 1, "c0_cacheerr,1" }, 306 { 27, 2, "c0_cacheerr,2" }, 307 { 27, 3, "c0_cacheerr,3" }, 308 { 28, 1, "c0_datalo" }, 309 { 28, 2, "c0_taglo1" }, 310 { 28, 3, "c0_datalo1" }, 311 { 28, 4, "c0_taglo2" }, 312 { 28, 5, "c0_datalo2" }, 313 { 28, 6, "c0_taglo3" }, 314 { 28, 7, "c0_datalo3" }, 315 { 29, 1, "c0_datahi" }, 316 { 29, 2, "c0_taghi1" }, 317 { 29, 3, "c0_datahi1" }, 318 { 29, 4, "c0_taghi2" }, 319 { 29, 5, "c0_datahi2" }, 320 { 29, 6, "c0_taghi3" }, 321 { 29, 7, "c0_datahi3" }, 322 }; 323 324 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ 325 static const char * const mips_cp0_names_sb1[32] = 326 { 327 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 328 "c0_context", "c0_pagemask", "c0_wired", "$7", 329 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 330 "c0_status", "c0_cause", "c0_epc", "c0_prid", 331 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 332 "c0_xcontext", "$21", "$22", "c0_debug", 333 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", 334 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", 335 }; 336 337 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = 338 { 339 { 16, 1, "c0_config1" }, 340 { 18, 1, "c0_watchlo,1" }, 341 { 19, 1, "c0_watchhi,1" }, 342 { 22, 0, "c0_perftrace" }, 343 { 23, 3, "c0_edebug" }, 344 { 25, 1, "c0_perfcnt,1" }, 345 { 25, 2, "c0_perfcnt,2" }, 346 { 25, 3, "c0_perfcnt,3" }, 347 { 25, 4, "c0_perfcnt,4" }, 348 { 25, 5, "c0_perfcnt,5" }, 349 { 25, 6, "c0_perfcnt,6" }, 350 { 25, 7, "c0_perfcnt,7" }, 351 { 26, 1, "c0_buserr_pa" }, 352 { 27, 1, "c0_cacheerr_d" }, 353 { 27, 3, "c0_cacheerr_d_pa" }, 354 { 28, 1, "c0_datalo_i" }, 355 { 28, 2, "c0_taglo_d" }, 356 { 28, 3, "c0_datalo_d" }, 357 { 29, 1, "c0_datahi_i" }, 358 { 29, 2, "c0_taghi_d" }, 359 { 29, 3, "c0_datahi_d" }, 360 }; 361 362 /* Xlr cop0 register names. */ 363 static const char * const mips_cp0_names_xlr[32] = { 364 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 365 "c0_context", "c0_pagemask", "c0_wired", "$7", 366 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 367 "c0_status", "c0_cause", "c0_epc", "c0_prid", 368 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 369 "c0_xcontext", "$21", "$22", "c0_debug", 370 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", 371 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", 372 }; 373 374 /* XLR's CP0 Select Registers. */ 375 376 static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = { 377 { 9, 6, "c0_extintreq" }, 378 { 9, 7, "c0_extintmask" }, 379 { 15, 1, "c0_ebase" }, 380 { 16, 1, "c0_config1" }, 381 { 16, 2, "c0_config2" }, 382 { 16, 3, "c0_config3" }, 383 { 16, 7, "c0_procid2" }, 384 { 18, 1, "c0_watchlo,1" }, 385 { 18, 2, "c0_watchlo,2" }, 386 { 18, 3, "c0_watchlo,3" }, 387 { 18, 4, "c0_watchlo,4" }, 388 { 18, 5, "c0_watchlo,5" }, 389 { 18, 6, "c0_watchlo,6" }, 390 { 18, 7, "c0_watchlo,7" }, 391 { 19, 1, "c0_watchhi,1" }, 392 { 19, 2, "c0_watchhi,2" }, 393 { 19, 3, "c0_watchhi,3" }, 394 { 19, 4, "c0_watchhi,4" }, 395 { 19, 5, "c0_watchhi,5" }, 396 { 19, 6, "c0_watchhi,6" }, 397 { 19, 7, "c0_watchhi,7" }, 398 { 25, 1, "c0_perfcnt,1" }, 399 { 25, 2, "c0_perfcnt,2" }, 400 { 25, 3, "c0_perfcnt,3" }, 401 { 25, 4, "c0_perfcnt,4" }, 402 { 25, 5, "c0_perfcnt,5" }, 403 { 25, 6, "c0_perfcnt,6" }, 404 { 25, 7, "c0_perfcnt,7" }, 405 { 27, 1, "c0_cacheerr,1" }, 406 { 27, 2, "c0_cacheerr,2" }, 407 { 27, 3, "c0_cacheerr,3" }, 408 { 28, 1, "c0_datalo" }, 409 { 29, 1, "c0_datahi" } 410 }; 411 412 static const char * const mips_hwr_names_numeric[32] = 413 { 414 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 415 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 416 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 417 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 418 }; 419 420 static const char * const mips_hwr_names_mips3264r2[32] = 421 { 422 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", 423 "$4", "$5", "$6", "$7", 424 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 425 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 426 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 427 }; 428 429 static const char * const msa_control_names[32] = 430 { 431 "msa_ir", "msa_csr", "msa_access", "msa_save", 432 "msa_modify", "msa_request", "msa_map", "msa_unmap", 433 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 434 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 435 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 436 }; 437 438 struct mips_abi_choice 439 { 440 const char * name; 441 const char * const *gpr_names; 442 const char * const *fpr_names; 443 }; 444 445 struct mips_abi_choice mips_abi_choices[] = 446 { 447 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, 448 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, 449 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, 450 { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, 451 }; 452 453 struct mips_arch_choice 454 { 455 const char *name; 456 int bfd_mach_valid; 457 unsigned long bfd_mach; 458 int processor; 459 int isa; 460 int ase; 461 const char * const *cp0_names; 462 const struct mips_cp0sel_name *cp0sel_names; 463 unsigned int cp0sel_names_len; 464 const char * const *cp1_names; 465 const char * const *hwr_names; 466 }; 467 468 const struct mips_arch_choice mips_arch_choices[] = 469 { 470 { "numeric", 0, 0, 0, 0, 0, 471 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 472 mips_hwr_names_numeric }, 473 474 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0, 475 mips_cp0_names_r3000, NULL, 0, mips_cp1_names_numeric, 476 mips_hwr_names_numeric }, 477 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0, 478 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 479 mips_hwr_names_numeric }, 480 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0, 481 mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric, 482 mips_hwr_names_numeric }, 483 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0, 484 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 485 mips_hwr_names_numeric }, 486 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0, 487 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 488 mips_hwr_names_numeric }, 489 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0, 490 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 491 mips_hwr_names_numeric }, 492 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0, 493 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 494 mips_hwr_names_numeric }, 495 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0, 496 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 497 mips_hwr_names_numeric }, 498 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0, 499 mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric, 500 mips_hwr_names_numeric }, 501 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0, 502 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 503 mips_hwr_names_numeric }, 504 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0, 505 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 506 mips_hwr_names_numeric }, 507 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0, 508 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 509 mips_hwr_names_numeric }, 510 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0, 511 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 512 mips_hwr_names_numeric }, 513 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0, 514 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 515 mips_hwr_names_numeric }, 516 { "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0, 517 mips_cp0_names_r5900, NULL, 0, mips_cp1_names_numeric, 518 mips_hwr_names_numeric }, 519 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0, 520 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 521 mips_hwr_names_numeric }, 522 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0, 523 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 524 mips_hwr_names_numeric }, 525 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0, 526 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 527 mips_hwr_names_numeric }, 528 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0, 529 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 530 mips_hwr_names_numeric }, 531 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0, 532 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 533 mips_hwr_names_numeric }, 534 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0, 535 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 536 mips_hwr_names_numeric }, 537 { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0, 538 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 539 mips_hwr_names_numeric }, 540 { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0, 541 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 542 mips_hwr_names_numeric }, 543 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0, 544 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 545 mips_hwr_names_numeric }, 546 547 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. 548 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See 549 _MIPS32 Architecture For Programmers Volume I: Introduction to the 550 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), 551 page 1. */ 552 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, 553 ISA_MIPS32, ASE_SMARTMIPS | ASE_MXU, 554 mips_cp0_names_mips3264, 555 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 556 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 557 558 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, 559 ISA_MIPS32R2, 560 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D 561 | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA | ASE_MXU), 562 mips_cp0_names_mips3264r2, 563 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 564 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 565 566 { "mips32r3", 1, bfd_mach_mipsisa32r3, CPU_MIPS32R3, 567 ISA_MIPS32R3, 568 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D 569 | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA | ASE_MXU), 570 mips_cp0_names_mips3264r2, 571 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 572 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 573 574 { "mips32r5", 1, bfd_mach_mipsisa32r5, CPU_MIPS32R5, 575 ISA_MIPS32R5, 576 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D 577 | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA | ASE_MXU), 578 mips_cp0_names_mips3264r2, 579 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 580 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 581 582 { "mips32r6", 1, bfd_mach_mipsisa32r6, CPU_MIPS32R6, 583 ISA_MIPS32R6, 584 (ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP 585 | ASE_DSPR2 | ASE_DSPR6), 586 mips_cp0_names_mips3264r2, 587 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 588 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 589 590 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ 591 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, 592 ISA_MIPS64, ASE_MIPS3D | ASE_MDMX | ASE_MXU, 593 mips_cp0_names_mips3264, 594 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 595 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 596 597 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, 598 ISA_MIPS64R2, 599 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT 600 | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA 601 | ASE_MXU), 602 mips_cp0_names_mips3264r2, 603 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 604 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 605 606 { "mips64r3", 1, bfd_mach_mipsisa64r3, CPU_MIPS64R3, 607 ISA_MIPS64R3, 608 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT 609 | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA 610 | ASE_MXU), 611 mips_cp0_names_mips3264r2, 612 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 613 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 614 615 { "mips64r5", 1, bfd_mach_mipsisa64r5, CPU_MIPS64R5, 616 ISA_MIPS64R5, 617 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT 618 | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA 619 | ASE_MXU), 620 mips_cp0_names_mips3264r2, 621 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 622 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 623 624 { "mips64r6", 1, bfd_mach_mipsisa64r6, CPU_MIPS64R6, 625 ISA_MIPS64R6, 626 (ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64 627 | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR6 | ASE_DSP64), 628 mips_cp0_names_mips3264r2, 629 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 630 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 631 632 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, 633 ISA_MIPS64 | INSN_SB1, ASE_MIPS3D, 634 mips_cp0_names_sb1, 635 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), 636 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 637 638 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E, 639 ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric, 640 NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, 641 642 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F, 643 ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric, 644 NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, 645 646 { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A, 647 ISA_MIPS64R2 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric, 648 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, 649 650 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON, 651 ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0, 652 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 653 654 { "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP, 655 ISA_MIPS64R2 | INSN_OCTEONP, 0, mips_cp0_names_numeric, 656 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, 657 658 { "octeon2", 1, bfd_mach_mips_octeon2, CPU_OCTEON2, 659 ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric, 660 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, 661 662 { "octeon3", 1, bfd_mach_mips_octeon3, CPU_OCTEON3, 663 ISA_MIPS64R5 | INSN_OCTEON3, ASE_VIRT | ASE_VIRT64, 664 mips_cp0_names_numeric, 665 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, 666 667 { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR, 668 ISA_MIPS64 | INSN_XLR, 0, 669 mips_cp0_names_xlr, 670 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), 671 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 672 673 /* XLP is mostly like XLR, with the prominent exception it is being 674 MIPS64R2. */ 675 { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR, 676 ISA_MIPS64R2 | INSN_XLR, 0, 677 mips_cp0_names_xlr, 678 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), 679 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 680 681 /* This entry, mips16, is here only for ISA/processor selection; do 682 not print its name. */ 683 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, 0, 684 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 685 mips_hwr_names_numeric }, 686 }; 687 688 /* ISA and processor type to disassemble for, and register names to use. 689 set_default_mips_dis_options and parse_mips_dis_options fill in these 690 values. */ 691 static int mips_processor; 692 static int mips_isa; 693 static int mips_ase; 694 static int micromips_ase; 695 static const char * const *mips_gpr_names; 696 static const char * const *mips_fpr_names; 697 static const char * const *mips_cp0_names; 698 static const struct mips_cp0sel_name *mips_cp0sel_names; 699 static int mips_cp0sel_names_len; 700 static const char * const *mips_cp1_names; 701 static const char * const *mips_hwr_names; 702 703 /* Other options */ 704 static int no_aliases; /* If set disassemble as most general inst. */ 705 706 static const struct mips_abi_choice * 708 choose_abi_by_name (const char *name, unsigned int namelen) 709 { 710 const struct mips_abi_choice *c; 711 unsigned int i; 712 713 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) 714 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 715 && strlen (mips_abi_choices[i].name) == namelen) 716 c = &mips_abi_choices[i]; 717 718 return c; 719 } 720 721 static const struct mips_arch_choice * 722 choose_arch_by_name (const char *name, unsigned int namelen) 723 { 724 const struct mips_arch_choice *c = NULL; 725 unsigned int i; 726 727 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 728 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 729 && strlen (mips_arch_choices[i].name) == namelen) 730 c = &mips_arch_choices[i]; 731 732 return c; 733 } 734 735 static const struct mips_arch_choice * 736 choose_arch_by_number (unsigned long mach) 737 { 738 static unsigned long hint_bfd_mach; 739 static const struct mips_arch_choice *hint_arch_choice; 740 const struct mips_arch_choice *c; 741 unsigned int i; 742 743 /* We optimize this because even if the user specifies no 744 flags, this will be done for every instruction! */ 745 if (hint_bfd_mach == mach 746 && hint_arch_choice != NULL 747 && hint_arch_choice->bfd_mach == hint_bfd_mach) 748 return hint_arch_choice; 749 750 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 751 { 752 if (mips_arch_choices[i].bfd_mach_valid 753 && mips_arch_choices[i].bfd_mach == mach) 754 { 755 c = &mips_arch_choices[i]; 756 hint_bfd_mach = mach; 757 hint_arch_choice = c; 758 } 759 } 760 return c; 761 } 762 763 /* Check if the object uses NewABI conventions. */ 764 765 static int 766 is_newabi (Elf_Internal_Ehdr *header) 767 { 768 /* There are no old-style ABIs which use 64-bit ELF. */ 769 if (header->e_ident[EI_CLASS] == ELFCLASS64) 770 return 1; 771 772 /* If a 32-bit ELF file, n32 is a new-style ABI. */ 773 if ((header->e_flags & EF_MIPS_ABI2) != 0) 774 return 1; 775 776 return 0; 777 } 778 779 /* Check if the object has microMIPS ASE code. */ 780 781 static int 782 is_micromips (Elf_Internal_Ehdr *header) 783 { 784 if ((header->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0) 785 return 1; 786 787 return 0; 788 } 789 790 /* Check if ISA is R6. */ 791 792 static inline int 793 is_isa_r6 (unsigned long isa) 794 { 795 if ((isa & INSN_ISA_MASK) == ISA_MIPS32R6 796 || ((isa & INSN_ISA_MASK) == ISA_MIPS64R6)) 797 return 1; 798 return 0; 799 } 800 801 static void 802 set_default_mips_dis_options (struct disassemble_info *info) 803 { 804 const struct mips_arch_choice *chosen_arch; 805 806 /* Defaults: mipsIII/r3000 (?!), no microMIPS ASE (any compressed code 807 is MIPS16 ASE) (o)32-style ("oldabi") GPR names, and numeric FPR, 808 CP0 register, and HWR names. */ 809 mips_isa = ISA_MIPS3; 810 mips_processor = CPU_R3000; 811 micromips_ase = 0; 812 mips_ase = 0; 813 mips_gpr_names = mips_gpr_names_oldabi; 814 mips_fpr_names = mips_fpr_names_numeric; 815 mips_cp0_names = mips_cp0_names_numeric; 816 mips_cp0sel_names = NULL; 817 mips_cp0sel_names_len = 0; 818 mips_cp1_names = mips_cp1_names_numeric; 819 mips_hwr_names = mips_hwr_names_numeric; 820 no_aliases = 0; 821 822 /* Update settings according to the ELF file header flags. */ 823 if (info->flavour == bfd_target_elf_flavour && info->section != NULL) 824 { 825 Elf_Internal_Ehdr *header; 826 827 header = elf_elfheader (info->section->owner); 828 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ 829 if (is_newabi (header)) 830 mips_gpr_names = mips_gpr_names_newabi; 831 /* If a microMIPS binary, then don't use MIPS16 bindings. */ 832 micromips_ase = is_micromips (header); 833 } 834 835 /* Set ISA, architecture, and cp0 register names as best we can. */ 836 #if ! SYMTAB_AVAILABLE 837 /* This is running out on a target machine, not in a host tool. 838 FIXME: Where does mips_target_info come from? */ 839 target_processor = mips_target_info.processor; 840 mips_isa = mips_target_info.isa; 841 mips_ase = mips_target_info.ase; 842 #else 843 chosen_arch = choose_arch_by_number (info->mach); 844 if (chosen_arch != NULL) 845 { 846 mips_processor = chosen_arch->processor; 847 mips_isa = chosen_arch->isa; 848 mips_ase = chosen_arch->ase; 849 mips_cp0_names = chosen_arch->cp0_names; 850 mips_cp0sel_names = chosen_arch->cp0sel_names; 851 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 852 mips_cp1_names = chosen_arch->cp1_names; 853 mips_hwr_names = chosen_arch->hwr_names; 854 } 855 #endif 856 } 857 858 static void 859 parse_mips_dis_option (const char *option, unsigned int len) 860 { 861 unsigned int i, optionlen, vallen; 862 const char *val; 863 const struct mips_abi_choice *chosen_abi; 864 const struct mips_arch_choice *chosen_arch; 865 866 /* Try to match options that are simple flags */ 867 if (CONST_STRNEQ (option, "no-aliases")) 868 { 869 no_aliases = 1; 870 return; 871 } 872 873 if (CONST_STRNEQ (option, "msa")) 874 { 875 mips_ase |= ASE_MSA; 876 if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2 877 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R3 878 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R5 879 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6) 880 mips_ase |= ASE_MSA64; 881 return; 882 } 883 884 if (CONST_STRNEQ (option, "virt")) 885 { 886 mips_ase |= ASE_VIRT; 887 if (mips_isa & ISA_MIPS64R2 888 || mips_isa & ISA_MIPS64R3 889 || mips_isa & ISA_MIPS64R5 890 || mips_isa & ISA_MIPS64R6) 891 mips_ase |= ASE_VIRT64; 892 return; 893 } 894 895 if (CONST_STRNEQ (option, "xpa")) 896 { 897 mips_ase |= ASE_XPA; 898 return; 899 } 900 901 if (CONST_STRNEQ (option, "mxu")) 902 { 903 mips_ase |= ASE_MXU; 904 return; 905 } 906 907 /* Look for the = that delimits the end of the option name. */ 908 for (i = 0; i < len; i++) 909 if (option[i] == '=') 910 break; 911 912 if (i == 0) /* Invalid option: no name before '='. */ 913 return; 914 if (i == len) /* Invalid option: no '='. */ 915 return; 916 if (i == (len - 1)) /* Invalid option: no value after '='. */ 917 return; 918 919 optionlen = i; 920 val = option + (optionlen + 1); 921 vallen = len - (optionlen + 1); 922 923 if (strncmp ("gpr-names", option, optionlen) == 0 924 && strlen ("gpr-names") == optionlen) 925 { 926 chosen_abi = choose_abi_by_name (val, vallen); 927 if (chosen_abi != NULL) 928 mips_gpr_names = chosen_abi->gpr_names; 929 return; 930 } 931 932 if (strncmp ("fpr-names", option, optionlen) == 0 933 && strlen ("fpr-names") == optionlen) 934 { 935 chosen_abi = choose_abi_by_name (val, vallen); 936 if (chosen_abi != NULL) 937 mips_fpr_names = chosen_abi->fpr_names; 938 return; 939 } 940 941 if (strncmp ("cp0-names", option, optionlen) == 0 942 && strlen ("cp0-names") == optionlen) 943 { 944 chosen_arch = choose_arch_by_name (val, vallen); 945 if (chosen_arch != NULL) 946 { 947 mips_cp0_names = chosen_arch->cp0_names; 948 mips_cp0sel_names = chosen_arch->cp0sel_names; 949 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 950 } 951 return; 952 } 953 954 if (strncmp ("cp1-names", option, optionlen) == 0 955 && strlen ("cp1-names") == optionlen) 956 { 957 chosen_arch = choose_arch_by_name (val, vallen); 958 if (chosen_arch != NULL) 959 mips_cp1_names = chosen_arch->cp1_names; 960 return; 961 } 962 963 if (strncmp ("hwr-names", option, optionlen) == 0 964 && strlen ("hwr-names") == optionlen) 965 { 966 chosen_arch = choose_arch_by_name (val, vallen); 967 if (chosen_arch != NULL) 968 mips_hwr_names = chosen_arch->hwr_names; 969 return; 970 } 971 972 if (strncmp ("reg-names", option, optionlen) == 0 973 && strlen ("reg-names") == optionlen) 974 { 975 /* We check both ABI and ARCH here unconditionally, so 976 that "numeric" will do the desirable thing: select 977 numeric register names for all registers. Other than 978 that, a given name probably won't match both. */ 979 chosen_abi = choose_abi_by_name (val, vallen); 980 if (chosen_abi != NULL) 981 { 982 mips_gpr_names = chosen_abi->gpr_names; 983 mips_fpr_names = chosen_abi->fpr_names; 984 } 985 chosen_arch = choose_arch_by_name (val, vallen); 986 if (chosen_arch != NULL) 987 { 988 mips_cp0_names = chosen_arch->cp0_names; 989 mips_cp0sel_names = chosen_arch->cp0sel_names; 990 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 991 mips_cp1_names = chosen_arch->cp1_names; 992 mips_hwr_names = chosen_arch->hwr_names; 993 } 994 return; 995 } 996 997 /* Invalid option. */ 998 } 999 1000 static void 1001 parse_mips_dis_options (const char *options) 1002 { 1003 const char *option_end; 1004 1005 if (options == NULL) 1006 return; 1007 1008 while (*options != '\0') 1009 { 1010 /* Skip empty options. */ 1011 if (*options == ',') 1012 { 1013 options++; 1014 continue; 1015 } 1016 1017 /* We know that *options is neither NUL or a comma. */ 1018 option_end = options + 1; 1019 while (*option_end != ',' && *option_end != '\0') 1020 option_end++; 1021 1022 parse_mips_dis_option (options, option_end - options); 1023 1024 /* Go on to the next one. If option_end points to a comma, it 1025 will be skipped above. */ 1026 options = option_end; 1027 } 1028 } 1029 1030 static const struct mips_cp0sel_name * 1031 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, 1032 unsigned int len, 1033 unsigned int cp0reg, 1034 unsigned int sel) 1035 { 1036 unsigned int i; 1037 1038 for (i = 0; i < len; i++) 1039 if (names[i].cp0reg == cp0reg && names[i].sel == sel) 1040 return &names[i]; 1041 return NULL; 1042 } 1043 1044 /* Print register REGNO, of type TYPE, for instruction OPCODE. */ 1045 1046 static void 1047 print_reg (struct disassemble_info *info, const struct mips_opcode *opcode, 1048 enum mips_reg_operand_type type, int regno) 1049 { 1050 switch (type) 1051 { 1052 case OP_REG_MXU: 1053 case OP_REG_MXU_GP: 1054 info->fprintf_func (info->stream, "%s", mips_gpr_names_xr[regno]); 1055 break; 1056 1057 case OP_REG_GP: 1058 info->fprintf_func (info->stream, "%s", mips_gpr_names[regno]); 1059 break; 1060 1061 case OP_REG_FP: 1062 info->fprintf_func (info->stream, "%s", mips_fpr_names[regno]); 1063 break; 1064 1065 case OP_REG_CCC: 1066 if (opcode->pinfo & (FP_D | FP_S)) 1067 info->fprintf_func (info->stream, "$fcc%d", regno); 1068 else 1069 info->fprintf_func (info->stream, "$cc%d", regno); 1070 break; 1071 1072 case OP_REG_VEC: 1073 if (opcode->membership & INSN_5400) 1074 info->fprintf_func (info->stream, "$f%d", regno); 1075 else 1076 info->fprintf_func (info->stream, "$v%d", regno); 1077 break; 1078 1079 case OP_REG_ACC: 1080 info->fprintf_func (info->stream, "$ac%d", regno); 1081 break; 1082 1083 case OP_REG_COPRO: 1084 if (opcode->name[strlen (opcode->name) - 1] == '0') 1085 info->fprintf_func (info->stream, "%s", mips_cp0_names[regno]); 1086 else if (opcode->name[strlen (opcode->name) - 1] == '1') 1087 info->fprintf_func (info->stream, "%s", mips_cp1_names[regno]); 1088 else 1089 info->fprintf_func (info->stream, "$%d", regno); 1090 break; 1091 1092 case OP_REG_HW: 1093 info->fprintf_func (info->stream, "%s", mips_hwr_names[regno]); 1094 break; 1095 1096 case OP_REG_VF: 1097 info->fprintf_func (info->stream, "$vf%d", regno); 1098 break; 1099 1100 case OP_REG_VI: 1101 info->fprintf_func (info->stream, "$vi%d", regno); 1102 break; 1103 1104 case OP_REG_R5900_I: 1105 info->fprintf_func (info->stream, "$I"); 1106 break; 1107 1108 case OP_REG_R5900_Q: 1109 info->fprintf_func (info->stream, "$Q"); 1110 break; 1111 1112 case OP_REG_R5900_R: 1113 info->fprintf_func (info->stream, "$R"); 1114 break; 1115 1116 case OP_REG_R5900_ACC: 1117 info->fprintf_func (info->stream, "$ACC"); 1118 break; 1119 1120 case OP_REG_MSA: 1121 info->fprintf_func (info->stream, "$w%d", regno); 1122 break; 1123 1124 case OP_REG_MSA_CTRL: 1125 info->fprintf_func (info->stream, "%s", msa_control_names[regno]); 1126 break; 1127 1128 } 1129 } 1130 1131 /* Used to track the state carried over from previous operands in 1133 an instruction. */ 1134 struct mips_print_arg_state { 1135 /* The value of the last OP_INT seen. We only use this for OP_MSB, 1136 where the value is known to be unsigned and small. */ 1137 unsigned int last_int; 1138 1139 /* The type and number of the last OP_REG seen. We only use this for 1140 OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG. */ 1141 enum mips_reg_operand_type last_reg_type; 1142 unsigned int last_regno; 1143 unsigned int dest_regno; 1144 unsigned int seen_dest; 1145 }; 1146 1147 /* Initialize STATE for the start of an instruction. */ 1148 1149 static inline void 1150 init_print_arg_state (struct mips_print_arg_state *state) 1151 { 1152 memset (state, 0, sizeof (*state)); 1153 } 1154 1155 /* Print OP_VU0_SUFFIX or OP_VU0_MATCH_SUFFIX operand OPERAND, 1156 whose value is given by UVAL. */ 1157 1158 static void 1159 print_vu0_channel (struct disassemble_info *info, 1160 const struct mips_operand *operand, unsigned int uval) 1161 { 1162 if (operand->size == 4) 1163 info->fprintf_func (info->stream, "%s%s%s%s", 1164 uval & 8 ? "x" : "", 1165 uval & 4 ? "y" : "", 1166 uval & 2 ? "z" : "", 1167 uval & 1 ? "w" : ""); 1168 else if (operand->size == 2) 1169 info->fprintf_func (info->stream, "%c", "xyzw"[uval]); 1170 else 1171 abort (); 1172 } 1173 1174 /* Record information about a register operand. */ 1175 1176 static void 1177 mips_seen_register (struct mips_print_arg_state *state, 1178 unsigned int regno, 1179 enum mips_reg_operand_type reg_type) 1180 { 1181 state->last_reg_type = reg_type; 1182 state->last_regno = regno; 1183 1184 if (!state->seen_dest) 1185 { 1186 state->seen_dest = 1; 1187 state->dest_regno = regno; 1188 } 1189 } 1190 1191 /* Print operand OPERAND of OPCODE, using STATE to track inter-operand state. 1192 UVAL is the encoding of the operand (shifted into bit 0) and BASE_PC is 1193 the base address for OP_PCREL operands. */ 1194 1195 static void 1196 print_insn_arg (struct disassemble_info *info, 1197 struct mips_print_arg_state *state, 1198 const struct mips_opcode *opcode, 1199 const struct mips_operand *operand, 1200 bfd_vma base_pc, 1201 unsigned int uval) 1202 { 1203 const fprintf_ftype infprintf = info->fprintf_func; 1204 void *is = info->stream; 1205 1206 switch (operand->type) 1207 { 1208 case OP_MAPPED_STRING: 1209 { 1210 const struct mips_mapped_string_operand *string_op; 1211 string_op = (const struct mips_mapped_string_operand *) operand; 1212 infprintf (is, "%s", string_op->strings[uval]); 1213 } 1214 break; 1215 case OP_INT: 1216 { 1217 const struct mips_int_operand *int_op; 1218 1219 int_op = (const struct mips_int_operand *) operand; 1220 uval = mips_decode_int_operand (int_op, uval); 1221 state->last_int = uval; 1222 if (int_op->print_hex) 1223 infprintf (is, "0x%x", uval); 1224 else 1225 infprintf (is, "%d", uval); 1226 } 1227 break; 1228 1229 case OP_MAPPED_INT: 1230 { 1231 const struct mips_mapped_int_operand *mint_op; 1232 1233 mint_op = (const struct mips_mapped_int_operand *) operand; 1234 uval = mint_op->int_map[uval]; 1235 state->last_int = uval; 1236 if (mint_op->print_hex) 1237 infprintf (is, "0x%x", uval); 1238 else 1239 infprintf (is, "%d", uval); 1240 } 1241 break; 1242 1243 case OP_MSB: 1244 { 1245 const struct mips_msb_operand *msb_op; 1246 1247 msb_op = (const struct mips_msb_operand *) operand; 1248 uval += msb_op->bias; 1249 if (msb_op->add_lsb) 1250 uval -= state->last_int; 1251 infprintf (is, "0x%x", uval); 1252 } 1253 break; 1254 1255 case OP_REG: 1256 case OP_OPTIONAL_REG: 1257 { 1258 const struct mips_reg_operand *reg_op; 1259 1260 reg_op = (const struct mips_reg_operand *) operand; 1261 uval = mips_decode_reg_operand (reg_op, uval); 1262 print_reg (info, opcode, reg_op->reg_type, uval); 1263 1264 mips_seen_register (state, uval, reg_op->reg_type); 1265 } 1266 break; 1267 1268 case OP_REG_PAIR: 1269 { 1270 const struct mips_reg_pair_operand *pair_op; 1271 1272 pair_op = (const struct mips_reg_pair_operand *) operand; 1273 print_reg (info, opcode, pair_op->reg_type, 1274 pair_op->reg1_map[uval]); 1275 infprintf (is, ","); 1276 print_reg (info, opcode, pair_op->reg_type, 1277 pair_op->reg2_map[uval]); 1278 } 1279 break; 1280 1281 case OP_PCREL: 1282 { 1283 const struct mips_pcrel_operand *pcrel_op; 1284 1285 pcrel_op = (const struct mips_pcrel_operand *) operand; 1286 info->target = mips_decode_pcrel_operand (pcrel_op, base_pc, uval); 1287 1288 /* Preserve the ISA bit for the GDB disassembler, 1289 otherwise clear it. */ 1290 if (info->flavour != bfd_target_unknown_flavour) 1291 info->target &= -2; 1292 1293 (*info->print_address_func) (info->target, info); 1294 } 1295 break; 1296 1297 case OP_PERF_REG: 1298 infprintf (is, "%d", uval); 1299 break; 1300 1301 case OP_ADDIUSP_INT: 1302 { 1303 int sval; 1304 1305 sval = mips_signed_operand (operand, uval) * 4; 1306 if (sval >= -8 && sval < 8) 1307 sval ^= 0x400; 1308 infprintf (is, "%d", sval); 1309 break; 1310 } 1311 1312 case OP_CLO_CLZ_DEST: 1313 { 1314 unsigned int reg1, reg2; 1315 1316 reg1 = uval & 31; 1317 reg2 = uval >> 5; 1318 /* If one is zero use the other. */ 1319 if (reg1 == reg2 || reg2 == 0) 1320 infprintf (is, "%s", mips_gpr_names[reg1]); 1321 else if (reg1 == 0) 1322 infprintf (is, "%s", mips_gpr_names[reg2]); 1323 else 1324 /* Bogus, result depends on processor. */ 1325 infprintf (is, "%s or %s", mips_gpr_names[reg1], 1326 mips_gpr_names[reg2]); 1327 } 1328 break; 1329 1330 case OP_SAME_RS_RT: 1331 case OP_CHECK_PREV: 1332 case OP_NON_ZERO_REG: 1333 { 1334 print_reg (info, opcode, OP_REG_GP, uval & 31); 1335 mips_seen_register (state, uval, OP_REG_GP); 1336 } 1337 break; 1338 1339 case OP_LWM_SWM_LIST: 1340 if (operand->size == 2) 1341 { 1342 if (uval == 0) 1343 infprintf (is, "%s,%s", 1344 mips_gpr_names[16], 1345 mips_gpr_names[31]); 1346 else 1347 infprintf (is, "%s-%s,%s", 1348 mips_gpr_names[16], 1349 mips_gpr_names[16 + uval], 1350 mips_gpr_names[31]); 1351 } 1352 else 1353 { 1354 int s_reg_encode; 1355 1356 s_reg_encode = uval & 0xf; 1357 if (s_reg_encode != 0) 1358 { 1359 if (s_reg_encode == 1) 1360 infprintf (is, "%s", mips_gpr_names[16]); 1361 else if (s_reg_encode < 9) 1362 infprintf (is, "%s-%s", 1363 mips_gpr_names[16], 1364 mips_gpr_names[15 + s_reg_encode]); 1365 else if (s_reg_encode == 9) 1366 infprintf (is, "%s-%s,%s", 1367 mips_gpr_names[16], 1368 mips_gpr_names[23], 1369 mips_gpr_names[30]); 1370 else 1371 infprintf (is, "UNKNOWN"); 1372 } 1373 1374 if (uval & 0x10) /* For ra. */ 1375 { 1376 if (s_reg_encode == 0) 1377 infprintf (is, "%s", mips_gpr_names[31]); 1378 else 1379 infprintf (is, ",%s", mips_gpr_names[31]); 1380 } 1381 } 1382 break; 1383 1384 case OP_ENTRY_EXIT_LIST: 1385 { 1386 const char *sep; 1387 unsigned int amask, smask; 1388 1389 sep = ""; 1390 amask = (uval >> 3) & 7; 1391 if (amask > 0 && amask < 5) 1392 { 1393 infprintf (is, "%s", mips_gpr_names[4]); 1394 if (amask > 1) 1395 infprintf (is, "-%s", mips_gpr_names[amask + 3]); 1396 sep = ","; 1397 } 1398 1399 smask = (uval >> 1) & 3; 1400 if (smask == 3) 1401 { 1402 infprintf (is, "%s??", sep); 1403 sep = ","; 1404 } 1405 else if (smask > 0) 1406 { 1407 infprintf (is, "%s%s", sep, mips_gpr_names[16]); 1408 if (smask > 1) 1409 infprintf (is, "-%s", mips_gpr_names[smask + 15]); 1410 sep = ","; 1411 } 1412 1413 if (uval & 1) 1414 { 1415 infprintf (is, "%s%s", sep, mips_gpr_names[31]); 1416 sep = ","; 1417 } 1418 1419 if (amask == 5 || amask == 6) 1420 { 1421 infprintf (is, "%s%s", sep, mips_fpr_names[0]); 1422 if (amask == 6) 1423 infprintf (is, "-%s", mips_fpr_names[1]); 1424 } 1425 } 1426 break; 1427 1428 case OP_SAVE_RESTORE_LIST: 1429 /* Should be handled by the caller due to extend behavior. */ 1430 abort (); 1431 1432 case OP_MDMX_IMM_REG: 1433 { 1434 unsigned int vsel; 1435 1436 vsel = uval >> 5; 1437 uval &= 31; 1438 if ((vsel & 0x10) == 0) 1439 { 1440 int fmt; 1441 1442 vsel &= 0x0f; 1443 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) 1444 if ((vsel & 1) == 0) 1445 break; 1446 print_reg (info, opcode, OP_REG_VEC, uval); 1447 infprintf (is, "[%d]", vsel >> 1); 1448 } 1449 else if ((vsel & 0x08) == 0) 1450 print_reg (info, opcode, OP_REG_VEC, uval); 1451 else 1452 infprintf (is, "0x%x", uval); 1453 } 1454 break; 1455 1456 case OP_REPEAT_PREV_REG: 1457 print_reg (info, opcode, state->last_reg_type, state->last_regno); 1458 break; 1459 1460 case OP_REPEAT_DEST_REG: 1461 print_reg (info, opcode, state->last_reg_type, state->dest_regno); 1462 break; 1463 1464 case OP_PC: 1465 infprintf (is, "$pc"); 1466 break; 1467 1468 case OP_VU0_SUFFIX: 1469 case OP_VU0_MATCH_SUFFIX: 1470 print_vu0_channel (info, operand, uval); 1471 break; 1472 1473 case OP_IMM_INDEX: 1474 infprintf (is, "[%d]", uval); 1475 break; 1476 1477 case OP_MXU_STRIDE: 1478 infprintf (is, "%d", uval); 1479 break; 1480 1481 case OP_REG_INDEX: 1482 infprintf (is, "["); 1483 print_reg (info, opcode, OP_REG_GP, uval); 1484 infprintf (is, "]"); 1485 break; 1486 } 1487 } 1488 1489 /* Validate the arguments for INSN, which is described by OPCODE. 1490 Use DECODE_OPERAND to get the encoding of each operand. */ 1491 1492 static bfd_boolean 1493 validate_insn_args (const struct mips_opcode *opcode, 1494 const struct mips_operand *(*decode_operand) (const char *), 1495 unsigned int insn) 1496 { 1497 struct mips_print_arg_state state; 1498 const struct mips_operand *operand; 1499 const char *s; 1500 unsigned int uval; 1501 1502 init_print_arg_state (&state); 1503 for (s = opcode->args; *s; ++s) 1504 { 1505 switch (*s) 1506 { 1507 case ',': 1508 case '(': 1509 case ')': 1510 break; 1511 1512 case '#': 1513 ++s; 1514 break; 1515 1516 default: 1517 operand = decode_operand (s); 1518 1519 if (operand) 1520 { 1521 uval = mips_extract_operand (operand, insn); 1522 switch (operand->type) 1523 { 1524 case OP_REG: 1525 case OP_OPTIONAL_REG: 1526 { 1527 const struct mips_reg_operand *reg_op; 1528 1529 reg_op = (const struct mips_reg_operand *) operand; 1530 uval = mips_decode_reg_operand (reg_op, uval); 1531 mips_seen_register (&state, uval, reg_op->reg_type); 1532 } 1533 break; 1534 1535 case OP_SAME_RS_RT: 1536 { 1537 unsigned int reg1, reg2; 1538 1539 reg1 = uval & 31; 1540 reg2 = uval >> 5; 1541 1542 if (reg1 != reg2 || reg1 == 0) 1543 return FALSE; 1544 } 1545 break; 1546 1547 case OP_CHECK_PREV: 1548 { 1549 const struct mips_check_prev_operand *prev_op; 1550 1551 prev_op = (const struct mips_check_prev_operand *) operand; 1552 1553 if (!prev_op->zero_ok && uval == 0) 1554 return FALSE; 1555 1556 if (((prev_op->less_than_ok && uval < state.last_regno) 1557 || (prev_op->greater_than_ok && uval > state.last_regno) 1558 || (prev_op->equal_ok && uval == state.last_regno))) 1559 break; 1560 1561 return FALSE; 1562 } 1563 1564 case OP_NON_ZERO_REG: 1565 { 1566 if (uval == 0) 1567 return FALSE; 1568 } 1569 break; 1570 1571 case OP_INT: 1572 case OP_MAPPED_INT: 1573 case OP_MSB: 1574 case OP_REG_PAIR: 1575 case OP_PCREL: 1576 case OP_PERF_REG: 1577 case OP_ADDIUSP_INT: 1578 case OP_CLO_CLZ_DEST: 1579 case OP_LWM_SWM_LIST: 1580 case OP_ENTRY_EXIT_LIST: 1581 case OP_MDMX_IMM_REG: 1582 case OP_REPEAT_PREV_REG: 1583 case OP_REPEAT_DEST_REG: 1584 case OP_PC: 1585 case OP_VU0_SUFFIX: 1586 case OP_VU0_MATCH_SUFFIX: 1587 case OP_IMM_INDEX: 1588 case OP_REG_INDEX: 1589 case OP_MXU_STRIDE: 1590 case OP_MAPPED_STRING: 1591 break; 1592 1593 case OP_SAVE_RESTORE_LIST: 1594 /* Should be handled by the caller due to extend behavior. */ 1595 abort (); 1596 } 1597 } 1598 if (*s == 'm' || *s == '+' || *s == '-' || *s == '`') 1599 ++s; 1600 } 1601 } 1602 return TRUE; 1603 } 1604 1605 /* Print the arguments for INSN, which is described by OPCODE. 1606 Use DECODE_OPERAND to get the encoding of each operand. Use BASE_PC 1607 as the base of OP_PCREL operands, adjusting by LENGTH if the OP_PCREL 1608 operand is for a branch or jump. */ 1609 1610 static void 1611 print_insn_args (struct disassemble_info *info, 1612 const struct mips_opcode *opcode, 1613 const struct mips_operand *(*decode_operand) (const char *), 1614 unsigned int insn, bfd_vma insn_pc, unsigned int length) 1615 { 1616 const fprintf_ftype infprintf = info->fprintf_func; 1617 void *is = info->stream; 1618 struct mips_print_arg_state state; 1619 const struct mips_operand *operand; 1620 const char *s; 1621 1622 init_print_arg_state (&state); 1623 for (s = opcode->args; *s; ++s) 1624 { 1625 switch (*s) 1626 { 1627 case ',': 1628 case '(': 1629 case ')': 1630 infprintf (is, "%c", *s); 1631 break; 1632 1633 case '#': 1634 ++s; 1635 infprintf (is, "%c%c", *s, *s); 1636 break; 1637 1638 default: 1639 operand = decode_operand (s); 1640 if (!operand) 1641 { 1642 /* xgettext:c-format */ 1643 infprintf (is, 1644 _("# internal error, undefined operand in `%s %s'"), 1645 opcode->name, opcode->args); 1646 return; 1647 } 1648 if (operand->type == OP_REG 1649 && s[1] == ',' 1650 && s[2] == 'H' 1651 && opcode->name[strlen (opcode->name) - 1] == '0') 1652 { 1653 /* Coprocessor register 0 with sel field (MT ASE). */ 1654 const struct mips_cp0sel_name *n; 1655 unsigned int reg, sel; 1656 1657 reg = mips_extract_operand (operand, insn); 1658 s += 2; 1659 operand = decode_operand (s); 1660 sel = mips_extract_operand (operand, insn); 1661 1662 /* CP0 register including 'sel' code for mftc0, to be 1663 printed textually if known. If not known, print both 1664 CP0 register name and sel numerically since CP0 register 1665 with sel 0 may have a name unrelated to register being 1666 printed. */ 1667 n = lookup_mips_cp0sel_name (mips_cp0sel_names, 1668 mips_cp0sel_names_len, 1669 reg, sel); 1670 if (n != NULL) 1671 infprintf (is, "%s", n->name); 1672 else 1673 infprintf (is, "$%d,%d", reg, sel); 1674 } 1675 else 1676 { 1677 bfd_vma base_pc = insn_pc; 1678 1679 /* Adjust the PC relative base so that branch/jump insns use 1680 the following PC as the base but genuinely PC relative 1681 operands use the current PC. */ 1682 if (operand->type == OP_PCREL) 1683 { 1684 const struct mips_pcrel_operand *pcrel_op; 1685 1686 pcrel_op = (const struct mips_pcrel_operand *) operand; 1687 /* The include_isa_bit flag is sufficient to distinguish 1688 branch/jump from other PC relative operands. */ 1689 if (pcrel_op->include_isa_bit) 1690 base_pc += length; 1691 } 1692 1693 print_insn_arg (info, &state, opcode, operand, base_pc, 1694 mips_extract_operand (operand, insn)); 1695 } 1696 if (*s == 'm' || *s == '+' || *s == '-' || *s == '`') 1697 ++s; 1698 break; 1699 } 1700 } 1701 } 1702 1703 /* Print the mips instruction at address MEMADDR in debugged memory, 1705 on using INFO. Returns length of the instruction, in bytes, which is 1706 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if 1707 this is little-endian code. */ 1708 1709 static int 1710 print_insn_mips (bfd_vma memaddr, 1711 int word, 1712 struct disassemble_info *info) 1713 { 1714 #define GET_OP(insn, field) \ 1715 (((insn) >> OP_SH_##field) & OP_MASK_##field) 1716 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; 1717 const fprintf_ftype infprintf = info->fprintf_func; 1718 const struct mips_opcode *op; 1719 static bfd_boolean init = 0; 1720 void *is = info->stream; 1721 1722 /* Build a hash table to shorten the search time. */ 1723 if (! init) 1724 { 1725 unsigned int i; 1726 1727 for (i = 0; i <= OP_MASK_OP; i++) 1728 { 1729 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) 1730 { 1731 if (op->pinfo == INSN_MACRO 1732 || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) 1733 continue; 1734 if (i == GET_OP (op->match, OP)) 1735 { 1736 mips_hash[i] = op; 1737 break; 1738 } 1739 } 1740 } 1741 1742 init = 1; 1743 } 1744 1745 info->bytes_per_chunk = INSNLEN; 1746 info->display_endian = info->endian; 1747 info->insn_info_valid = 1; 1748 info->branch_delay_insns = 0; 1749 info->data_size = 0; 1750 info->insn_type = dis_nonbranch; 1751 info->target = 0; 1752 info->target2 = 0; 1753 1754 op = mips_hash[GET_OP (word, OP)]; 1755 if (op != NULL) 1756 { 1757 for (; op < &mips_opcodes[NUMOPCODES]; op++) 1758 { 1759 if (op->pinfo != INSN_MACRO 1760 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 1761 && (word & op->mask) == op->match) 1762 { 1763 /* We always disassemble the jalx instruction, except for MIPS r6. */ 1764 if ((!opcode_is_member (op, mips_isa, mips_ase, mips_processor) 1765 && (strcmp (op->name, "jalx") || is_isa_r6 (mips_isa))) 1766 || (is_isa_r6 (op->membership) 1767 && (op->pinfo2 & INSN2_CONVERTED_TO_COMPACT))) 1768 continue; 1769 1770 /* Figure out instruction type and branch delay information. */ 1771 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 1772 { 1773 if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_1)) != 0) 1774 info->insn_type = dis_jsr; 1775 else 1776 info->insn_type = dis_branch; 1777 info->branch_delay_insns = 1; 1778 } 1779 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY 1780 | INSN_COND_BRANCH_LIKELY)) != 0) 1781 { 1782 if ((op->pinfo & INSN_WRITE_GPR_31) != 0) 1783 info->insn_type = dis_condjsr; 1784 else 1785 info->insn_type = dis_condbranch; 1786 info->branch_delay_insns = 1; 1787 } 1788 else if ((op->pinfo & (INSN_STORE_MEMORY 1789 | INSN_LOAD_MEMORY)) != 0) 1790 info->insn_type = dis_dref; 1791 1792 if (!validate_insn_args (op, decode_mips_operand, word)) 1793 continue; 1794 1795 infprintf (is, "%s", op->name); 1796 if (op->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) 1797 { 1798 unsigned int uval; 1799 1800 infprintf (is, "."); 1801 uval = mips_extract_operand (&mips_vu0_channel_mask, word); 1802 print_vu0_channel (info, &mips_vu0_channel_mask, uval); 1803 } 1804 1805 if (op->args[0]) 1806 { 1807 infprintf (is, "\t"); 1808 print_insn_args (info, op, decode_mips_operand, word, 1809 memaddr, 4); 1810 } 1811 1812 return INSNLEN; 1813 } 1814 } 1815 } 1816 #undef GET_OP 1817 1818 /* Handle undefined instructions. */ 1819 info->insn_type = dis_noninsn; 1820 infprintf (is, "0x%x", word); 1821 return INSNLEN; 1822 } 1823 1824 /* Disassemble an operand for a mips16 instruction. */ 1826 1827 static void 1828 print_mips16_insn_arg (struct disassemble_info *info, 1829 struct mips_print_arg_state *state, 1830 const struct mips_opcode *opcode, 1831 char type, bfd_vma memaddr, 1832 unsigned insn, bfd_boolean use_extend, 1833 unsigned extend, bfd_boolean is_offset) 1834 { 1835 const fprintf_ftype infprintf = info->fprintf_func; 1836 void *is = info->stream; 1837 const struct mips_operand *operand, *ext_operand; 1838 unsigned int uval; 1839 bfd_vma baseaddr; 1840 1841 if (!use_extend) 1842 extend = 0; 1843 1844 switch (type) 1845 { 1846 case ',': 1847 case '(': 1848 case ')': 1849 infprintf (is, "%c", type); 1850 break; 1851 1852 default: 1853 operand = decode_mips16_operand (type, FALSE); 1854 if (!operand) 1855 { 1856 /* xgettext:c-format */ 1857 infprintf (is, _("# internal error, undefined operand in `%s %s'"), 1858 opcode->name, opcode->args); 1859 return; 1860 } 1861 1862 if (operand->type == OP_SAVE_RESTORE_LIST) 1863 { 1864 /* Handle this case here because of the complex interation 1865 with the EXTEND opcode. */ 1866 unsigned int amask, nargs, nstatics, nsreg, smask, frame_size, i, j; 1867 const char *sep; 1868 1869 amask = extend & 0xf; 1870 if (amask == MIPS16_ALL_ARGS) 1871 { 1872 nargs = 4; 1873 nstatics = 0; 1874 } 1875 else if (amask == MIPS16_ALL_STATICS) 1876 { 1877 nargs = 0; 1878 nstatics = 4; 1879 } 1880 else 1881 { 1882 nargs = amask >> 2; 1883 nstatics = amask & 3; 1884 } 1885 1886 sep = ""; 1887 if (nargs > 0) 1888 { 1889 infprintf (is, "%s", mips_gpr_names[4]); 1890 if (nargs > 1) 1891 infprintf (is, "-%s", mips_gpr_names[4 + nargs - 1]); 1892 sep = ","; 1893 } 1894 1895 frame_size = ((extend & 0xf0) | (insn & 0x0f)) * 8; 1896 if (frame_size == 0 && !use_extend) 1897 frame_size = 128; 1898 infprintf (is, "%s%d", sep, frame_size); 1899 1900 if (insn & 0x40) /* $ra */ 1901 infprintf (is, ",%s", mips_gpr_names[31]); 1902 1903 nsreg = (extend >> 8) & 0x7; 1904 smask = 0; 1905 if (insn & 0x20) /* $s0 */ 1906 smask |= 1 << 0; 1907 if (insn & 0x10) /* $s1 */ 1908 smask |= 1 << 1; 1909 if (nsreg > 0) /* $s2-$s8 */ 1910 smask |= ((1 << nsreg) - 1) << 2; 1911 1912 for (i = 0; i < 9; i++) 1913 if (smask & (1 << i)) 1914 { 1915 infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]); 1916 /* Skip over string of set bits. */ 1917 for (j = i; smask & (2 << j); j++) 1918 continue; 1919 if (j > i) 1920 infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]); 1921 i = j + 1; 1922 } 1923 /* Statics $ax - $a3. */ 1924 if (nstatics == 1) 1925 infprintf (is, ",%s", mips_gpr_names[7]); 1926 else if (nstatics > 0) 1927 infprintf (is, ",%s-%s", 1928 mips_gpr_names[7 - nstatics + 1], 1929 mips_gpr_names[7]); 1930 break; 1931 } 1932 1933 if (is_offset && operand->type == OP_INT) 1934 { 1935 const struct mips_int_operand *int_op; 1936 1937 int_op = (const struct mips_int_operand *) operand; 1938 info->insn_type = dis_dref; 1939 info->data_size = 1 << int_op->shift; 1940 } 1941 1942 if (operand->size == 26) 1943 /* In this case INSN is the first two bytes of the instruction 1944 and EXTEND is the second two bytes. */ 1945 uval = ((insn & 0x1f) << 21) | ((insn & 0x3e0) << 11) | extend; 1946 else 1947 { 1948 /* Calculate the full field value. */ 1949 uval = mips_extract_operand (operand, insn); 1950 if (use_extend) 1951 { 1952 ext_operand = decode_mips16_operand (type, TRUE); 1953 if (ext_operand != operand) 1954 { 1955 operand = ext_operand; 1956 if (operand->size == 16) 1957 uval |= ((extend & 0x1f) << 11) | (extend & 0x7e0); 1958 else if (operand->size == 15) 1959 uval |= ((extend & 0xf) << 11) | (extend & 0x7f0); 1960 else 1961 uval = ((extend >> 6) & 0x1f) | (extend & 0x20); 1962 } 1963 } 1964 } 1965 1966 baseaddr = memaddr + 2; 1967 if (operand->type == OP_PCREL) 1968 { 1969 const struct mips_pcrel_operand *pcrel_op; 1970 1971 pcrel_op = (const struct mips_pcrel_operand *) operand; 1972 if (!pcrel_op->include_isa_bit && use_extend) 1973 baseaddr = memaddr - 2; 1974 else if (!pcrel_op->include_isa_bit) 1975 { 1976 bfd_byte buffer[2]; 1977 1978 /* If this instruction is in the delay slot of a JR 1979 instruction, the base address is the address of the 1980 JR instruction. If it is in the delay slot of a JALR 1981 instruction, the base address is the address of the 1982 JALR instruction. This test is unreliable: we have 1983 no way of knowing whether the previous word is 1984 instruction or data. */ 1985 if (info->read_memory_func (memaddr - 4, buffer, 2, info) == 0 1986 && (((info->endian == BFD_ENDIAN_BIG 1987 ? bfd_getb16 (buffer) 1988 : bfd_getl16 (buffer)) 1989 & 0xf800) == 0x1800)) 1990 baseaddr = memaddr - 4; 1991 else if (info->read_memory_func (memaddr - 2, buffer, 2, 1992 info) == 0 1993 && (((info->endian == BFD_ENDIAN_BIG 1994 ? bfd_getb16 (buffer) 1995 : bfd_getl16 (buffer)) 1996 & 0xf81f) == 0xe800)) 1997 baseaddr = memaddr - 2; 1998 else 1999 baseaddr = memaddr; 2000 } 2001 } 2002 2003 print_insn_arg (info, state, opcode, operand, baseaddr + 1, uval); 2004 break; 2005 } 2006 } 2007 2008 2009 /* Check if the given address is the last word of a MIPS16 PLT entry. 2010 This word is data and depending on the value it may interfere with 2011 disassembly of further PLT entries. We make use of the fact PLT 2012 symbols are marked BSF_SYNTHETIC. */ 2013 static bfd_boolean 2014 is_mips16_plt_tail (struct disassemble_info *info, bfd_vma addr) 2015 { 2016 if (info->symbols 2017 && info->symbols[0] 2018 && (info->symbols[0]->flags & BSF_SYNTHETIC) 2019 && addr == bfd_asymbol_value (info->symbols[0]) + 12) 2020 return TRUE; 2021 2022 return FALSE; 2023 } 2024 2025 /* Disassemble mips16 instructions. */ 2026 2027 static int 2028 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) 2029 { 2030 const fprintf_ftype infprintf = info->fprintf_func; 2031 int status; 2032 bfd_byte buffer[4]; 2033 int length; 2034 int insn; 2035 bfd_boolean use_extend; 2036 int extend = 0; 2037 const struct mips_opcode *op, *opend; 2038 struct mips_print_arg_state state; 2039 void *is = info->stream; 2040 2041 info->bytes_per_chunk = 2; 2042 info->display_endian = info->endian; 2043 info->insn_info_valid = 1; 2044 info->branch_delay_insns = 0; 2045 info->data_size = 0; 2046 info->target = 0; 2047 info->target2 = 0; 2048 2049 #define GET_OP(insn, field) \ 2050 (((insn) >> MIPS16OP_SH_##field) & MIPS16OP_MASK_##field) 2051 /* Decode PLT entry's GOT slot address word. */ 2052 if (is_mips16_plt_tail (info, memaddr)) 2053 { 2054 info->insn_type = dis_noninsn; 2055 status = (*info->read_memory_func) (memaddr, buffer, 4, info); 2056 if (status == 0) 2057 { 2058 unsigned int gotslot; 2059 2060 if (info->endian == BFD_ENDIAN_BIG) 2061 gotslot = bfd_getb32 (buffer); 2062 else 2063 gotslot = bfd_getl32 (buffer); 2064 infprintf (is, ".word\t0x%x", gotslot); 2065 2066 return 4; 2067 } 2068 } 2069 else 2070 { 2071 info->insn_type = dis_nonbranch; 2072 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 2073 } 2074 if (status != 0) 2075 { 2076 (*info->memory_error_func) (status, memaddr, info); 2077 return -1; 2078 } 2079 2080 length = 2; 2081 2082 if (info->endian == BFD_ENDIAN_BIG) 2083 insn = bfd_getb16 (buffer); 2084 else 2085 insn = bfd_getl16 (buffer); 2086 2087 /* Handle the extend opcode specially. */ 2088 use_extend = FALSE; 2089 if ((insn & 0xf800) == 0xf000) 2090 { 2091 use_extend = TRUE; 2092 extend = insn & 0x7ff; 2093 2094 memaddr += 2; 2095 2096 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 2097 if (status != 0) 2098 { 2099 infprintf (is, "extend 0x%x", (unsigned int) extend); 2100 (*info->memory_error_func) (status, memaddr, info); 2101 return -1; 2102 } 2103 2104 if (info->endian == BFD_ENDIAN_BIG) 2105 insn = bfd_getb16 (buffer); 2106 else 2107 insn = bfd_getl16 (buffer); 2108 2109 /* Check for an extend opcode followed by an extend opcode. */ 2110 if ((insn & 0xf800) == 0xf000) 2111 { 2112 infprintf (is, "extend 0x%x", (unsigned int) extend); 2113 info->insn_type = dis_noninsn; 2114 return length; 2115 } 2116 2117 length += 2; 2118 } 2119 2120 /* FIXME: Should probably use a hash table on the major opcode here. */ 2121 2122 opend = mips16_opcodes + bfd_mips16_num_opcodes; 2123 for (op = mips16_opcodes; op < opend; op++) 2124 { 2125 if (op->pinfo != INSN_MACRO 2126 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 2127 && (insn & op->mask) == op->match) 2128 { 2129 const char *s; 2130 2131 if (op->args[0] == 'a' || op->args[0] == 'i') 2132 { 2133 if (use_extend) 2134 { 2135 infprintf (is, "extend 0x%x", (unsigned int) extend); 2136 info->insn_type = dis_noninsn; 2137 return length - 2; 2138 } 2139 2140 use_extend = FALSE; 2141 2142 memaddr += 2; 2143 2144 status = (*info->read_memory_func) (memaddr, buffer, 2, 2145 info); 2146 if (status == 0) 2147 { 2148 use_extend = TRUE; 2149 if (info->endian == BFD_ENDIAN_BIG) 2150 extend = bfd_getb16 (buffer); 2151 else 2152 extend = bfd_getl16 (buffer); 2153 length += 2; 2154 } 2155 } 2156 2157 infprintf (is, "%s", op->name); 2158 if (op->args[0] != '\0') 2159 infprintf (is, "\t"); 2160 2161 init_print_arg_state (&state); 2162 for (s = op->args; *s != '\0'; s++) 2163 { 2164 if (*s == ',' 2165 && s[1] == 'w' 2166 && GET_OP (insn, RX) == GET_OP (insn, RY)) 2167 { 2168 /* Skip the register and the comma. */ 2169 ++s; 2170 continue; 2171 } 2172 if (*s == ',' 2173 && s[1] == 'v' 2174 && GET_OP (insn, RZ) == GET_OP (insn, RX)) 2175 { 2176 /* Skip the register and the comma. */ 2177 ++s; 2178 continue; 2179 } 2180 print_mips16_insn_arg (info, &state, op, *s, memaddr, insn, 2181 use_extend, extend, s[1] == '('); 2182 } 2183 2184 /* Figure out branch instruction type and delay slot information. */ 2185 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 2186 info->branch_delay_insns = 1; 2187 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 2188 || (op->pinfo2 & INSN2_UNCOND_BRANCH) != 0) 2189 { 2190 if ((op->pinfo & INSN_WRITE_GPR_31) != 0) 2191 info->insn_type = dis_jsr; 2192 else 2193 info->insn_type = dis_branch; 2194 } 2195 else if ((op->pinfo2 & INSN2_COND_BRANCH) != 0) 2196 info->insn_type = dis_condbranch; 2197 2198 return length; 2199 } 2200 } 2201 #undef GET_OP 2202 2203 if (use_extend) 2204 infprintf (is, "0x%x", extend | 0xf000); 2205 infprintf (is, "0x%x", insn); 2206 info->insn_type = dis_noninsn; 2207 2208 return length; 2209 } 2210 2211 /* Disassemble microMIPS instructions. */ 2212 2213 static int 2214 print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) 2215 { 2216 const fprintf_ftype infprintf = info->fprintf_func; 2217 const struct mips_opcode *op, *opend; 2218 void *is = info->stream; 2219 bfd_byte buffer[2]; 2220 unsigned int higher; 2221 unsigned int length; 2222 int status; 2223 unsigned int insn; 2224 2225 info->bytes_per_chunk = 2; 2226 info->display_endian = info->endian; 2227 info->insn_info_valid = 1; 2228 info->branch_delay_insns = 0; 2229 info->data_size = 0; 2230 info->insn_type = dis_nonbranch; 2231 info->target = 0; 2232 info->target2 = 0; 2233 2234 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 2235 if (status != 0) 2236 { 2237 (*info->memory_error_func) (status, memaddr, info); 2238 return -1; 2239 } 2240 2241 length = 2; 2242 2243 if (info->endian == BFD_ENDIAN_BIG) 2244 insn = bfd_getb16 (buffer); 2245 else 2246 insn = bfd_getl16 (buffer); 2247 2248 if ((insn & 0xfc00) == 0x7c00) 2249 { 2250 /* This is a 48-bit microMIPS instruction. */ 2251 higher = insn; 2252 2253 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); 2254 if (status != 0) 2255 { 2256 infprintf (is, "micromips 0x%x", higher); 2257 (*info->memory_error_func) (status, memaddr + 2, info); 2258 return -1; 2259 } 2260 if (info->endian == BFD_ENDIAN_BIG) 2261 insn = bfd_getb16 (buffer); 2262 else 2263 insn = bfd_getl16 (buffer); 2264 higher = (higher << 16) | insn; 2265 2266 status = (*info->read_memory_func) (memaddr + 4, buffer, 2, info); 2267 if (status != 0) 2268 { 2269 infprintf (is, "micromips 0x%x", higher); 2270 (*info->memory_error_func) (status, memaddr + 4, info); 2271 return -1; 2272 } 2273 if (info->endian == BFD_ENDIAN_BIG) 2274 insn = bfd_getb16 (buffer); 2275 else 2276 insn = bfd_getl16 (buffer); 2277 infprintf (is, "0x%x%04x (48-bit insn)", higher, insn); 2278 2279 info->insn_type = dis_noninsn; 2280 return 6; 2281 } 2282 else if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000) 2283 { 2284 /* This is a 32-bit microMIPS instruction. */ 2285 higher = insn; 2286 2287 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); 2288 if (status != 0) 2289 { 2290 infprintf (is, "micromips 0x%x", higher); 2291 (*info->memory_error_func) (status, memaddr + 2, info); 2292 return -1; 2293 } 2294 2295 if (info->endian == BFD_ENDIAN_BIG) 2296 insn = bfd_getb16 (buffer); 2297 else 2298 insn = bfd_getl16 (buffer); 2299 2300 insn = insn | (higher << 16); 2301 2302 length += 2; 2303 } 2304 2305 /* FIXME: Should probably use a hash table on the major opcode here. */ 2306 2307 opend = micromips_opcodes + bfd_micromips_num_opcodes; 2308 for (op = micromips_opcodes; op < opend; op++) 2309 { 2310 if (op->pinfo != INSN_MACRO 2311 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 2312 && (insn & op->mask) == op->match 2313 && ((length == 2 && (op->mask & 0xffff0000) == 0) 2314 || (length == 4 && (op->mask & 0xffff0000) != 0))) 2315 { 2316 if (!validate_insn_args (op, decode_micromips_operand, insn)) 2317 continue; 2318 2319 infprintf (is, "%s", op->name); 2320 2321 if (op->args[0]) 2322 { 2323 infprintf (is, "\t"); 2324 print_insn_args (info, op, decode_micromips_operand, insn, 2325 memaddr + 1, length); 2326 } 2327 2328 /* Figure out instruction type and branch delay information. */ 2329 if ((op->pinfo 2330 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY)) != 0) 2331 info->branch_delay_insns = 1; 2332 if (((op->pinfo & INSN_UNCOND_BRANCH_DELAY) 2333 | (op->pinfo2 & INSN2_UNCOND_BRANCH)) != 0) 2334 { 2335 if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_1)) != 0) 2336 info->insn_type = dis_jsr; 2337 else 2338 info->insn_type = dis_branch; 2339 } 2340 else if (((op->pinfo & INSN_COND_BRANCH_DELAY) 2341 | (op->pinfo2 & INSN2_COND_BRANCH)) != 0) 2342 { 2343 if ((op->pinfo & INSN_WRITE_GPR_31) != 0) 2344 info->insn_type = dis_condjsr; 2345 else 2346 info->insn_type = dis_condbranch; 2347 } 2348 else if ((op->pinfo 2349 & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY)) != 0) 2350 info->insn_type = dis_dref; 2351 2352 return length; 2353 } 2354 } 2355 2356 infprintf (is, "0x%x", insn); 2357 info->insn_type = dis_noninsn; 2358 2359 return length; 2360 } 2361 2362 /* Return 1 if a symbol associated with the location being disassembled 2363 indicates a compressed (MIPS16 or microMIPS) mode. We iterate over 2364 all the symbols at the address being considered assuming if at least 2365 one of them indicates code compression, then such code has been 2366 genuinely produced here (other symbols could have been derived from 2367 function symbols defined elsewhere or could define data). Otherwise, 2368 return 0. */ 2369 2370 static bfd_boolean 2371 is_compressed_mode_p (struct disassemble_info *info) 2372 { 2373 int i; 2374 int l; 2375 2376 for (i = info->symtab_pos, l = i + info->num_symbols; i < l; i++) 2377 if (((info->symtab[i])->flags & BSF_SYNTHETIC) != 0 2378 && ((!micromips_ase 2379 && ELF_ST_IS_MIPS16 ((*info->symbols)->udata.i)) 2380 || (micromips_ase 2381 && ELF_ST_IS_MICROMIPS ((*info->symbols)->udata.i)))) 2382 return 1; 2383 else if (bfd_asymbol_flavour (info->symtab[i]) == bfd_target_elf_flavour 2384 && info->symtab[i]->section == info->section) 2385 { 2386 elf_symbol_type *symbol = (elf_symbol_type *) info->symtab[i]; 2387 if ((!micromips_ase 2388 && ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other)) 2389 || (micromips_ase 2390 && ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other))) 2391 return 1; 2392 } 2393 2394 return 0; 2395 } 2396 2397 /* In an environment where we do not know the symbol type of the 2398 instruction we are forced to assume that the low order bit of the 2399 instructions' address may mark it as a mips16 instruction. If we 2400 are single stepping, or the pc is within the disassembled function, 2401 this works. Otherwise, we need a clue. Sometimes. */ 2402 2403 static int 2404 _print_insn_mips (bfd_vma memaddr, 2405 struct disassemble_info *info, 2406 enum bfd_endian endianness) 2407 { 2408 int (*print_insn_compr) (bfd_vma, struct disassemble_info *); 2409 bfd_byte buffer[INSNLEN]; 2410 int status; 2411 2412 set_default_mips_dis_options (info); 2413 parse_mips_dis_options (info->disassembler_options); 2414 2415 if (info->mach == bfd_mach_mips16) 2416 return print_insn_mips16 (memaddr, info); 2417 if (info->mach == bfd_mach_mips_micromips) 2418 return print_insn_micromips (memaddr, info); 2419 2420 print_insn_compr = !micromips_ase ? print_insn_mips16 : print_insn_micromips; 2421 2422 #if 1 2423 /* FIXME: If odd address, this is CLEARLY a compressed instruction. */ 2424 /* Only a few tools will work this way. */ 2425 if (memaddr & 0x01) 2426 return print_insn_compr (memaddr, info); 2427 #endif 2428 2429 #if SYMTAB_AVAILABLE 2430 if (is_compressed_mode_p (info)) 2431 return print_insn_compr (memaddr, info); 2432 #endif 2433 2434 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); 2435 if (status == 0) 2436 { 2437 int insn; 2438 2439 if (endianness == BFD_ENDIAN_BIG) 2440 insn = bfd_getb32 (buffer); 2441 else 2442 insn = bfd_getl32 (buffer); 2443 2444 return print_insn_mips (memaddr, insn, info); 2445 } 2446 else 2447 { 2448 (*info->memory_error_func) (status, memaddr, info); 2449 return -1; 2450 } 2451 } 2452 2453 int 2454 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info) 2455 { 2456 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); 2457 } 2458 2459 int 2460 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info) 2461 { 2462 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); 2463 } 2464 2465 void 2467 print_mips_disassembler_options (FILE *stream) 2468 { 2469 unsigned int i; 2470 2471 fprintf (stream, _("\n\ 2472 The following MIPS specific disassembler options are supported for use\n\ 2473 with the -M switch (multiple options should be separated by commas):\n")); 2474 2475 fprintf (stream, _("\n\ 2476 msa Recognize MSA instructions.\n")); 2477 2478 fprintf (stream, _("\n\ 2479 virt Recognize the virtualization ASE instructions.\n")); 2480 2481 fprintf (stream, _("\n\ 2482 xpa Recognize the eXtended Physical Address (XPA) ASE instructions.\n")); 2483 2484 fprintf (stream, _("\n\ 2485 mxu Recognize the MXU ASE instructions.\n")); 2486 2487 fprintf (stream, _("\n\ 2488 gpr-names=ABI Print GPR names according to specified ABI.\n\ 2489 Default: based on binary being disassembled.\n")); 2490 2491 fprintf (stream, _("\n\ 2492 fpr-names=ABI Print FPR names according to specified ABI.\n\ 2493 Default: numeric.\n")); 2494 2495 fprintf (stream, _("\n\ 2496 cp0-names=ARCH Print CP0 register names according to\n\ 2497 specified architecture.\n\ 2498 Default: based on binary being disassembled.\n")); 2499 2500 fprintf (stream, _("\n\ 2501 hwr-names=ARCH Print HWR names according to specified \n\ 2502 architecture.\n\ 2503 Default: based on binary being disassembled.\n")); 2504 2505 fprintf (stream, _("\n\ 2506 reg-names=ABI Print GPR and FPR names according to\n\ 2507 specified ABI.\n")); 2508 2509 fprintf (stream, _("\n\ 2510 reg-names=ARCH Print CP0 register and HWR names according to\n\ 2511 specified architecture.\n")); 2512 2513 fprintf (stream, _("\n\ 2514 For the options above, the following values are supported for \"ABI\":\n\ 2515 ")); 2516 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) 2517 fprintf (stream, " %s", mips_abi_choices[i].name); 2518 fprintf (stream, _("\n")); 2519 2520 fprintf (stream, _("\n\ 2521 For the options above, The following values are supported for \"ARCH\":\n\ 2522 ")); 2523 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) 2524 if (*mips_arch_choices[i].name != '\0') 2525 fprintf (stream, " %s", mips_arch_choices[i].name); 2526 fprintf (stream, _("\n")); 2527 2528 fprintf (stream, _("\n")); 2529 } 2530
