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      1 /*
      2 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
      3 *
      4 * Redistribution and use in source and binary forms, with or without modification, are permitted
      5 * provided that the following conditions are met:
      6 *    * Redistributions of source code must retain the above copyright notice, this list of
      7 *      conditions and the following disclaimer.
      8 *    * Redistributions in binary form must reproduce the above copyright notice, this list of
      9 *      conditions and the following disclaimer in the documentation and/or other materials provided
     10 *      with the distribution.
     11 *    * Neither the name of The Linux Foundation nor the names of its contributors may be used to
     12 *      endorse or promote products derived from this software without specific prior written
     13 *      permission.
     14 *
     15 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
     16 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     17 * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
     18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     21 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     22 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     23 */
     24 
     25 #ifndef __HW_INFO_TYPES_H__
     26 #define __HW_INFO_TYPES_H__
     27 
     28 #include <stdint.h>
     29 #include <core/display_interface.h>
     30 #include <core/core_interface.h>
     31 #include <vector>
     32 #include <map>
     33 #include <string>
     34 #include <bitset>
     35 
     36 namespace sdm {
     37 using std::string;
     38 
     39 const int kMaxSDELayers = 16;   // Maximum number of layers that can be handled by hardware in a
     40                                 // given layer stack.
     41 #define MAX_PLANES 4
     42 
     43 #define MAX_DETAIL_ENHANCE_CURVE 3
     44 
     45 enum HWDeviceType {
     46   kDevicePrimary,
     47   kDeviceHDMI,
     48   kDeviceVirtual,
     49   kDeviceRotator,
     50   kDeviceMax,
     51 };
     52 
     53 enum HWBlockType {
     54   kHWPrimary,
     55   kHWHDMI,
     56   kHWWriteback0,
     57   kHWWriteback1,
     58   kHWWriteback2,
     59   kHWBlockMax
     60 };
     61 
     62 enum HWDisplayMode {
     63   kModeDefault,
     64   kModeVideo,
     65   kModeCommand,
     66 };
     67 
     68 enum PipeType {
     69   kPipeTypeUnused,
     70   kPipeTypeVIG,
     71   kPipeTypeRGB,
     72   kPipeTypeDMA,
     73   kPipeTypeCursor,
     74 };
     75 
     76 enum HWSubBlockType {
     77   kHWVIGPipe,
     78   kHWRGBPipe,
     79   kHWDMAPipe,
     80   kHWCursorPipe,
     81   kHWRotatorInput,
     82   kHWRotatorOutput,
     83   kHWWBIntfOutput,
     84   kHWDestinationScalar,
     85   kHWSubBlockMax,
     86 };
     87 
     88 enum HWAlphaInterpolation {
     89   kInterpolationPixelRepeat,
     90   kInterpolationBilinear,
     91   kInterpolationMax,
     92 };
     93 
     94 enum HWBlendingFilter {
     95   kBlendFilterCircular,
     96   kBlendFilterSeparable,
     97   kBlendFilterMax,
     98 };
     99 
    100 enum HWPipeFlags {
    101   kIGC = 0x01,
    102   kMultiRect = 0x02,
    103   kMultiRectParallelMode = 0x04,
    104 };
    105 
    106 enum HWAVRModes {
    107   kContinuousMode,  // Mode to enable AVR feature for every frame.
    108   kOneShotMode,     // Mode to enable AVR feature for particular frame.
    109 };
    110 
    111 typedef std::map<HWSubBlockType, std::vector<LayerBufferFormat>> FormatsMap;
    112 
    113 struct HWDynBwLimitInfo {
    114   uint32_t cur_mode = kBwDefault;
    115   uint32_t total_bw_limit[kBwModeMax] = { 0 };
    116   uint32_t pipe_bw_limit[kBwModeMax] = { 0 };
    117 };
    118 
    119 struct HWPipeCaps {
    120   PipeType type = kPipeTypeUnused;
    121   uint32_t id = 0;
    122   uint32_t max_rects = 1;
    123 };
    124 
    125 struct HWRotatorInfo {
    126   enum { ROT_TYPE_MDSS, ROT_TYPE_V4L2 };
    127   uint32_t type = ROT_TYPE_MDSS;
    128   uint32_t num_rotator = 0;
    129   bool has_downscale = false;
    130   std::string device_path = "";
    131 
    132   void Reset() { *this = HWRotatorInfo(); }
    133 };
    134 
    135 struct HWDestScalarInfo {
    136   uint32_t count = 0;
    137   uint32_t max_input_width = 0;
    138   uint32_t max_output_width = 0;
    139   uint32_t max_scale_up = 1;
    140 };
    141 
    142 struct HWResourceInfo {
    143   uint32_t hw_version = 0;
    144   uint32_t hw_revision = 0;
    145   uint32_t num_dma_pipe = 0;
    146   uint32_t num_vig_pipe = 0;
    147   uint32_t num_rgb_pipe = 0;
    148   uint32_t num_cursor_pipe = 0;
    149   uint32_t num_blending_stages = 0;
    150   uint32_t num_control = 0;
    151   uint32_t num_mixer_to_disp = 0;
    152   uint32_t smp_total = 0;
    153   uint32_t smp_size = 0;
    154   uint32_t num_smp_per_pipe = 0;
    155   uint32_t max_scale_up = 1;
    156   uint32_t max_scale_down = 1;
    157   uint64_t max_bandwidth_low = 0;
    158   uint64_t max_bandwidth_high = 0;
    159   uint32_t max_mixer_width = 2048;
    160   uint32_t max_pipe_width = 2048;
    161   uint32_t max_cursor_size = 0;
    162   uint32_t max_pipe_bw =  0;
    163   uint32_t max_sde_clk = 0;
    164   float clk_fudge_factor = 1.0f;
    165   uint32_t macrotile_nv12_factor = 0;
    166   uint32_t macrotile_factor = 0;
    167   uint32_t linear_factor = 0;
    168   uint32_t scale_factor = 0;
    169   uint32_t extra_fudge_factor = 0;
    170   uint32_t amortizable_threshold = 0;
    171   uint32_t system_overhead_lines = 0;
    172   bool has_bwc = false;
    173   bool has_ubwc = false;
    174   bool has_decimation = false;
    175   bool has_macrotile = false;
    176   bool has_non_scalar_rgb = false;
    177   bool is_src_split = false;
    178   bool perf_calc = false;
    179   bool has_dyn_bw_support = false;
    180   bool separate_rotator = false;
    181   bool has_qseed3 = false;
    182   bool has_concurrent_writeback = false;
    183   uint32_t writeback_index = kHWBlockMax;
    184   HWDynBwLimitInfo dyn_bw_info;
    185   std::vector<HWPipeCaps> hw_pipes;
    186   FormatsMap supported_formats_map;
    187   HWRotatorInfo hw_rot_info;
    188   HWDestScalarInfo hw_dest_scalar_info;
    189   bool has_avr = false;
    190 
    191   void Reset() { *this = HWResourceInfo(); }
    192 };
    193 
    194 struct HWSplitInfo {
    195   uint32_t left_split = 0;
    196   uint32_t right_split = 0;
    197 
    198   bool operator !=(const HWSplitInfo &split_info) {
    199     return ((left_split != split_info.left_split) || (right_split != split_info.right_split));
    200   }
    201 
    202   bool operator ==(const HWSplitInfo &split_info) {
    203     return !(operator !=(split_info));
    204   }
    205 };
    206 
    207 enum HWS3DMode {
    208   kS3DModeNone,
    209   kS3DModeLR,
    210   kS3DModeRL,
    211   kS3DModeTB,
    212   kS3DModeFP,
    213   kS3DModeMax,
    214 };
    215 
    216 struct HWPanelInfo {
    217   DisplayPort port = kPortDefault;    // Display port
    218   HWDisplayMode mode = kModeDefault;  // Display mode
    219   bool partial_update = false;        // Partial update feature
    220   int left_align = 0;                 // ROI left alignment restriction
    221   int width_align = 0;                // ROI width alignment restriction
    222   int top_align = 0;                  // ROI top alignment restriction
    223   int height_align = 0;               // ROI height alignment restriction
    224   int min_roi_width = 0;              // Min width needed for ROI
    225   int min_roi_height = 0;             // Min height needed for ROI
    226   bool needs_roi_merge = false;       // Merge ROI's of both the DSI's
    227   bool dynamic_fps = false;           // Panel Supports dynamic fps
    228   bool dfps_porch_mode = false;       // dynamic fps VFP or HFP mode
    229   bool ping_pong_split = false;       // Supports Ping pong split
    230   uint32_t min_fps = 0;               // Min fps supported by panel
    231   uint32_t max_fps = 0;               // Max fps supported by panel
    232   bool is_primary_panel = false;      // Panel is primary display
    233   bool is_pluggable = false;          // Panel is pluggable
    234   HWSplitInfo split_info;             // Panel split configuration
    235   char panel_name[256] = {0};         // Panel name
    236   HWS3DMode s3d_mode = kS3DModeNone;  // Panel's current s3d mode.
    237   int panel_max_brightness = 0;       // Max panel brightness
    238 
    239   bool operator !=(const HWPanelInfo &panel_info) {
    240     return ((port != panel_info.port) || (mode != panel_info.mode) ||
    241             (partial_update != panel_info.partial_update) ||
    242             (left_align != panel_info.left_align) || (width_align != panel_info.width_align) ||
    243             (top_align != panel_info.top_align) || (height_align != panel_info.height_align) ||
    244             (min_roi_width != panel_info.min_roi_width) ||
    245             (min_roi_height != panel_info.min_roi_height) ||
    246             (needs_roi_merge != panel_info.needs_roi_merge) ||
    247             (dynamic_fps != panel_info.dynamic_fps) || (min_fps != panel_info.min_fps) ||
    248             (dfps_porch_mode != panel_info.dfps_porch_mode) ||
    249             (ping_pong_split != panel_info.ping_pong_split) ||
    250             (max_fps != panel_info.max_fps) || (is_primary_panel != panel_info.is_primary_panel) ||
    251             (split_info != panel_info.split_info) ||
    252             (s3d_mode != panel_info.s3d_mode));
    253   }
    254 
    255   bool operator ==(const HWPanelInfo &panel_info) {
    256     return !(operator !=(panel_info));
    257   }
    258 };
    259 
    260 struct HWSessionConfig {
    261   LayerRect src_rect;
    262   LayerRect dst_rect;
    263   uint32_t buffer_count = 0;
    264   bool secure = false;
    265   uint32_t frame_rate = 0;
    266   LayerTransform transform;
    267 
    268   bool operator==(const HWSessionConfig& config) const {
    269     return (src_rect == config.src_rect &&
    270             dst_rect == config.dst_rect &&
    271             buffer_count == config.buffer_count &&
    272             secure == config.secure &&
    273             frame_rate == config.frame_rate &&
    274             transform == config.transform);
    275   }
    276 
    277   bool operator!=(const HWSessionConfig& config) const {
    278     return !operator==(config);
    279   }
    280 };
    281 
    282 struct HWRotateInfo {
    283   int pipe_id = -1;  // Not actual pipe id, but the relative DMA id
    284   int writeback_id = -1;  // Writeback block id, but this is the same as DMA id
    285   LayerRect src_roi;  // Source crop of each split
    286   LayerRect dst_roi;  // Destination crop of each split
    287   bool valid = false;
    288   int rotate_id = -1;  // Actual rotator session id with driver
    289 
    290   void Reset() { *this = HWRotateInfo(); }
    291 };
    292 
    293 struct HWRotatorSession {
    294   HWRotateInfo hw_rotate_info[kMaxRotatePerLayer];
    295   uint32_t hw_block_count = 0;  // number of rotator hw blocks used by rotator session
    296   int session_id = -1;  // A handle with Session Manager
    297   HWSessionConfig hw_session_config;
    298   LayerBuffer input_buffer;  // Input to rotator
    299   LayerBuffer output_buffer;  // Output of rotator, crop width and stride are same
    300   float input_compression = 1.0f;
    301   float output_compression = 1.0f;
    302   bool is_buffer_cached = false;
    303 };
    304 
    305 struct HWScaleLutInfo {
    306   uint32_t dir_lut_size = 0;
    307   uint32_t cir_lut_size = 0;
    308   uint32_t sep_lut_size = 0;
    309   uint64_t dir_lut = 0;
    310   uint64_t cir_lut = 0;
    311   uint64_t sep_lut = 0;
    312 };
    313 
    314 struct HWDetailEnhanceData : DisplayDetailEnhancerData {
    315   uint16_t prec_shift = 0;
    316   int16_t adjust_a[MAX_DETAIL_ENHANCE_CURVE] = {0};
    317   int16_t adjust_b[MAX_DETAIL_ENHANCE_CURVE] = {0};
    318   int16_t adjust_c[MAX_DETAIL_ENHANCE_CURVE] = {0};
    319 };
    320 
    321 struct HWPixelExtension {
    322   int32_t extension = 0;  // Number of pixels extension in left, right, top and bottom directions
    323                           // for all color components. This pixel value for each color component
    324                           // should be sum of fetch and repeat pixels.
    325 
    326   int32_t overfetch = 0;  // Number of pixels need to be overfetched in left, right, top and bottom
    327                           // directions from source image for scaling.
    328 
    329   int32_t repeat = 0;     // Number of pixels need to be repeated in left, right, top and bottom
    330                           // directions for scaling.
    331 };
    332 
    333 struct HWPlane {
    334   int32_t init_phase_x = 0;
    335   int32_t phase_step_x = 0;
    336   int32_t init_phase_y = 0;
    337   int32_t phase_step_y = 0;
    338   HWPixelExtension left;
    339   HWPixelExtension top;
    340   HWPixelExtension right;
    341   HWPixelExtension bottom;
    342   uint32_t roi_width = 0;
    343   int32_t preload_x = 0;
    344   int32_t preload_y = 0;
    345   uint32_t src_width = 0;
    346   uint32_t src_height = 0;
    347 };
    348 
    349 struct HWScaleData {
    350   struct enable {
    351     uint8_t scale = 0;
    352     uint8_t direction_detection = 0;
    353     uint8_t detail_enhance = 0;
    354   } enable;
    355   uint32_t dst_width = 0;
    356   uint32_t dst_height = 0;
    357   HWPlane plane[MAX_PLANES];
    358   // scale_v2_data fields
    359   ScalingFilterConfig y_rgb_filter_cfg = kFilterEdgeDirected;
    360   ScalingFilterConfig uv_filter_cfg = kFilterEdgeDirected;
    361   HWAlphaInterpolation alpha_filter_cfg = kInterpolationPixelRepeat;
    362   HWBlendingFilter blend_cfg = kBlendFilterCircular;
    363 
    364   struct lut_flags {
    365     uint8_t lut_swap = 0;
    366     uint8_t lut_dir_wr = 0;
    367     uint8_t lut_y_cir_wr = 0;
    368     uint8_t lut_uv_cir_wr = 0;
    369     uint8_t lut_y_sep_wr = 0;
    370     uint8_t lut_uv_sep_wr = 0;
    371   } lut_flag;
    372 
    373   uint32_t dir_lut_idx = 0;
    374   /* for Y(RGB) and UV planes*/
    375   uint32_t y_rgb_cir_lut_idx = 0;
    376   uint32_t uv_cir_lut_idx = 0;
    377   uint32_t y_rgb_sep_lut_idx = 0;
    378   uint32_t uv_sep_lut_idx = 0;
    379 
    380   HWDetailEnhanceData detail_enhance;
    381 };
    382 
    383 struct HWDestScaleInfo {
    384   uint32_t mixer_width = 0;
    385   uint32_t mixer_height = 0;
    386   bool scale_update = false;
    387   HWScaleData scale_data = {};
    388 };
    389 
    390 typedef std::map<uint32_t, HWDestScaleInfo *> DestScaleInfoMap;
    391 
    392 struct HWAVRInfo {
    393   bool enable = false;                // Flag to Enable AVR feature
    394   HWAVRModes mode = kContinuousMode;  // Specifies the AVR mode
    395 };
    396 
    397 struct HWPipeInfo {
    398   uint32_t pipe_id = 0;
    399   HWSubBlockType sub_block_type = kHWSubBlockMax;
    400   LayerRect src_roi;
    401   LayerRect dst_roi;
    402   uint8_t horizontal_decimation = 0;
    403   uint8_t vertical_decimation = 0;
    404   HWScaleData scale_data;
    405   uint32_t z_order = 0;
    406   uint8_t flags = 0;
    407   bool valid = false;
    408 
    409   void Reset() { *this = HWPipeInfo(); }
    410 };
    411 
    412 struct HWLayerConfig {
    413   HWPipeInfo left_pipe;           // pipe for left side of output
    414   HWPipeInfo right_pipe;          // pipe for right side of output
    415   HWRotatorSession hw_rotator_session;
    416   float compression = 1.0f;
    417 
    418   void Reset() { *this = HWLayerConfig(); }
    419 };
    420 
    421 struct HWLayersInfo {
    422   LayerStack *stack = NULL;        // Input layer stack. Set by the caller.
    423   uint32_t app_layer_count = 0;    // Total number of app layers. Must not be 0.
    424   uint32_t gpu_target_index = 0;   // GPU target layer index. 0 if not present.
    425 
    426   uint32_t index[kMaxSDELayers];   // Indexes of the layers from the layer stack which need to be
    427                                    // programmed on hardware.
    428   LayerRect updated_src_rect[kMaxSDELayers];  // Updated layer src rects in s3d mode
    429   LayerRect updated_dst_rect[kMaxSDELayers];  // Updated layer dst rects in s3d mode
    430   bool updating[kMaxSDELayers] = {0};  // Updated by strategy, considering plane_alpha+updating
    431 
    432   uint32_t count = 0;              // Total number of layers which need to be set on hardware.
    433 
    434   int sync_handle = -1;
    435 
    436   LayerRect left_partial_update;   // Left ROI.
    437   LayerRect right_partial_update;  // Right ROI.
    438 
    439   bool use_hw_cursor = false;      // Indicates that HWCursor pipe needs to be used for cursor layer
    440   DestScaleInfoMap dest_scale_info_map = {};
    441 };
    442 
    443 struct HWLayers {
    444   HWLayersInfo info;
    445   HWLayerConfig config[kMaxSDELayers];
    446   float output_compression = 1.0f;
    447   uint32_t bandwidth = 0;
    448   uint32_t clock = 0;
    449   HWAVRInfo hw_avr_info = {};
    450 };
    451 
    452 struct HWDisplayAttributes : DisplayConfigVariableInfo {
    453   bool is_device_split = false;
    454   uint32_t v_front_porch = 0;  //!< Vertical front porch of panel
    455   uint32_t v_back_porch = 0;   //!< Vertical back porch of panel
    456   uint32_t v_pulse_width = 0;  //!< Vertical pulse width of panel
    457   uint32_t h_total = 0;        //!< Total width of panel (hActive + hFP + hBP + hPulseWidth)
    458   std::bitset<32> s3d_config;  //!< Stores the bit mask of S3D modes
    459 
    460   void Reset() { *this = HWDisplayAttributes(); }
    461 
    462   bool operator !=(const HWDisplayAttributes &display_attributes) {
    463     return ((is_device_split != display_attributes.is_device_split) ||
    464             (x_pixels != display_attributes.x_pixels) ||
    465             (y_pixels != display_attributes.y_pixels) ||
    466             (x_dpi != display_attributes.x_dpi) ||
    467             (y_dpi != display_attributes.y_dpi) ||
    468             (fps != display_attributes.fps) ||
    469             (vsync_period_ns != display_attributes.vsync_period_ns) ||
    470             (v_front_porch != display_attributes.v_front_porch) ||
    471             (v_back_porch != display_attributes.v_back_porch) ||
    472             (v_pulse_width != display_attributes.v_pulse_width) ||
    473             (is_yuv != display_attributes.is_yuv));
    474   }
    475 
    476   bool operator ==(const HWDisplayAttributes &display_attributes) {
    477     return !(operator !=(display_attributes));
    478   }
    479 };
    480 
    481 struct HWMixerAttributes {
    482   uint32_t width = 0;                                  // Layer mixer width
    483   uint32_t height = 0;                                 // Layer mixer height
    484   uint32_t split_left = 0;
    485   LayerBufferFormat output_format = kFormatRGB101010;  // Layer mixer output format
    486 
    487   bool operator !=(const HWMixerAttributes &mixer_attributes) {
    488     return ((width != mixer_attributes.width) ||
    489             (height != mixer_attributes.height) ||
    490             (output_format != mixer_attributes.output_format) ||
    491             (split_left != mixer_attributes.split_left));
    492   }
    493 
    494   bool operator ==(const HWMixerAttributes &mixer_attributes) {
    495     return !(operator !=(mixer_attributes));
    496   }
    497 
    498   bool IsValid() {
    499     return (width > 0 && height > 0);
    500   }
    501 };
    502 
    503 }  // namespace sdm
    504 
    505 #endif  // __HW_INFO_TYPES_H__
    506 
    507