1 /* Opcode table for the TI MSP430 microcontrollers 2 3 Copyright (C) 2002-2014 Free Software Foundation, Inc. 4 Contributed by Dmitry Diky <diwil (at) mail.ru> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21 #ifndef __MSP430_H_ 22 #define __MSP430_H_ 23 24 struct msp430_operand_s 25 { 26 int ol; /* Operand length words. */ 27 int am; /* Addr mode. */ 28 int reg; /* Register. */ 29 int mode; /* Operand mode. */ 30 int vshift; /* Number of bytes to shift operand down. */ 31 #define OP_REG 0 32 #define OP_EXP 1 33 #ifndef DASM_SECTION 34 expressionS exp; 35 #endif 36 }; 37 38 #define BYTE_OPERATION (1 << 6) /* Byte operation flag for all instructions. */ 39 40 struct msp430_opcode_s 41 { 42 char *name; 43 int fmt; 44 int insn_opnumb; 45 int bin_opcode; 46 int bin_mask; 47 }; 48 49 #define MSP_INSN(name, size, numb, bin, mask) { #name, size, numb, bin, mask } 50 51 static struct msp430_opcode_s msp430_opcodes[] = 52 { 53 MSP_INSN (and, 1, 2, 0xf000, 0xf000), 54 MSP_INSN (inv, 0, 1, 0xe330, 0xfff0), 55 MSP_INSN (xor, 1, 2, 0xe000, 0xf000), 56 MSP_INSN (setz, 0, 0, 0xd322, 0xffff), 57 MSP_INSN (setc, 0, 0, 0xd312, 0xffff), 58 MSP_INSN (eint, 0, 0, 0xd232, 0xffff), 59 MSP_INSN (setn, 0, 0, 0xd222, 0xffff), 60 MSP_INSN (bis, 1, 2, 0xd000, 0xf000), 61 MSP_INSN (clrz, 0, 0, 0xc322, 0xffff), 62 MSP_INSN (clrc, 0, 0, 0xc312, 0xffff), 63 MSP_INSN (dint, 0, 0, 0xc232, 0xffff), 64 MSP_INSN (clrn, 0, 0, 0xc222, 0xffff), 65 MSP_INSN (bic, 1, 2, 0xc000, 0xf000), 66 MSP_INSN (bit, 1, 2, 0xb000, 0xf000), 67 MSP_INSN (dadc, 0, 1, 0xa300, 0xff30), 68 MSP_INSN (dadd, 1, 2, 0xa000, 0xf000), 69 MSP_INSN (tst, 0, 1, 0x9300, 0xff30), 70 MSP_INSN (cmp, 1, 2, 0x9000, 0xf000), 71 MSP_INSN (decd, 0, 1, 0x8320, 0xff30), 72 MSP_INSN (dec, 0, 1, 0x8310, 0xff30), 73 MSP_INSN (sub, 1, 2, 0x8000, 0xf000), 74 MSP_INSN (sbc, 0, 1, 0x7300, 0xff30), 75 MSP_INSN (subc, 1, 2, 0x7000, 0xf000), 76 MSP_INSN (adc, 0, 1, 0x6300, 0xff30), 77 MSP_INSN (rlc, 0, 2, 0x6000, 0xf000), 78 MSP_INSN (addc, 1, 2, 0x6000, 0xf000), 79 MSP_INSN (incd, 0, 1, 0x5320, 0xff30), 80 MSP_INSN (inc, 0, 1, 0x5310, 0xff30), 81 MSP_INSN (rla, 0, 2, 0x5000, 0xf000), 82 MSP_INSN (add, 1, 2, 0x5000, 0xf000), 83 MSP_INSN (nop, 0, 0, 0x4303, 0xffff), 84 MSP_INSN (clr, 0, 1, 0x4300, 0xff30), 85 MSP_INSN (ret, 0, 0, 0x4130, 0xff30), 86 MSP_INSN (pop, 0, 1, 0x4130, 0xff30), 87 MSP_INSN (br, 0, 3, 0x4000, 0xf000), 88 MSP_INSN (mov, 1, 2, 0x4000, 0xf000), 89 MSP_INSN (jmp, 3, 1, 0x3c00, 0xfc00), 90 MSP_INSN (jl, 3, 1, 0x3800, 0xfc00), 91 MSP_INSN (jge, 3, 1, 0x3400, 0xfc00), 92 MSP_INSN (jn, 3, 1, 0x3000, 0xfc00), 93 MSP_INSN (jc, 3, 1, 0x2c00, 0xfc00), 94 MSP_INSN (jhs, 3, 1, 0x2c00, 0xfc00), 95 MSP_INSN (jnc, 3, 1, 0x2800, 0xfc00), 96 MSP_INSN (jlo, 3, 1, 0x2800, 0xfc00), 97 MSP_INSN (jz, 3, 1, 0x2400, 0xfc00), 98 MSP_INSN (jeq, 3, 1, 0x2400, 0xfc00), 99 MSP_INSN (jnz, 3, 1, 0x2000, 0xfc00), 100 MSP_INSN (jne, 3, 1, 0x2000, 0xfc00), 101 MSP_INSN (reti, 2, 0, 0x1300, 0xffc0), 102 MSP_INSN (call, 2, 1, 0x1280, 0xffc0), 103 MSP_INSN (push, 2, 1, 0x1200, 0xff80), 104 MSP_INSN (sxt, 2, 1, 0x1180, 0xffc0), 105 MSP_INSN (rra, 2, 1, 0x1100, 0xff80), 106 MSP_INSN (swpb, 2, 1, 0x1080, 0xffc0), 107 MSP_INSN (rrc, 2, 1, 0x1000, 0xff80), 108 /* Simple polymorphs. */ 109 MSP_INSN (beq, 4, 0, 0, 0xffff), 110 MSP_INSN (bne, 4, 1, 0, 0xffff), 111 MSP_INSN (blt, 4, 2, 0, 0xffff), 112 MSP_INSN (bltu, 4, 3, 0, 0xffff), 113 MSP_INSN (bge, 4, 4, 0, 0xffff), 114 MSP_INSN (bgeu, 4, 5, 0, 0xffff), 115 MSP_INSN (bltn, 4, 6, 0, 0xffff), 116 MSP_INSN (jump, 4, 7, 0, 0xffff), 117 /* Long polymorphs. */ 118 MSP_INSN (bgt, 5, 0, 0, 0xffff), 119 MSP_INSN (bgtu, 5, 1, 0, 0xffff), 120 MSP_INSN (bleu, 5, 2, 0, 0xffff), 121 MSP_INSN (ble, 5, 3, 0, 0xffff), 122 123 /* MSP430X instructions - these ones use an extension word. 124 A negative format indicates an MSP430X instruction. */ 125 MSP_INSN (addcx, -2, 2, 0x6000, 0xf000), 126 MSP_INSN (addx, -2, 2, 0x5000, 0xf000), 127 MSP_INSN (andx, -2, 2, 0xf000, 0xf000), 128 MSP_INSN (bicx, -2, 2, 0xc000, 0xf000), 129 MSP_INSN (bisx, -2, 2, 0xd000, 0xf000), 130 MSP_INSN (bitx, -2, 2, 0xb000, 0xf000), 131 MSP_INSN (cmpx, -2, 2, 0x9000, 0xf000), 132 MSP_INSN (daddx, -2, 2, 0xa000, 0xf000), 133 MSP_INSN (movx, -2, 2, 0x4000, 0xf000), 134 MSP_INSN (subcx, -2, 2, 0x7000, 0xf000), 135 MSP_INSN (subx, -2, 2, 0x8000, 0xf000), 136 MSP_INSN (xorx, -2, 2, 0xe000, 0xf000), 137 138 /* MSP430X Synthetic instructions. */ 139 MSP_INSN (adcx, -1, 1, 0x6300, 0xff30), 140 MSP_INSN (clra, -1, 1, 0x4300, 0xff30), 141 MSP_INSN (clrx, -1, 1, 0x4300, 0xff30), 142 MSP_INSN (dadcx, -1, 1, 0xa300, 0xff30), 143 MSP_INSN (decx, -1, 1, 0x8310, 0xff30), 144 MSP_INSN (decda, -1, 1, 0x8320, 0xff30), 145 MSP_INSN (decdx, -1, 1, 0x8320, 0xff30), 146 MSP_INSN (incx, -1, 1, 0x5310, 0xff30), 147 MSP_INSN (incda, -1, 1, 0x5320, 0xff30), 148 MSP_INSN (incdx, -1, 1, 0x5320, 0xff30), 149 MSP_INSN (invx, -1, 1, 0xe330, 0xfff0), 150 MSP_INSN (popx, -1, 1, 0x4130, 0xff30), 151 MSP_INSN (rlax, -1, 2, 0x5000, 0xf000), 152 MSP_INSN (rlcx, -1, 2, 0x6000, 0xf000), 153 MSP_INSN (sbcx, -1, 1, 0x7300, 0xff30), 154 MSP_INSN (tsta, -1, 1, 0x9300, 0xff30), 155 MSP_INSN (tstx, -1, 1, 0x9300, 0xff30), 156 157 MSP_INSN (pushx, -3, 1, 0x1200, 0xff80), 158 MSP_INSN (rrax, -3, 1, 0x1100, 0xff80), 159 MSP_INSN (rrcx, -3, 1, 0x1000, 0xff80), 160 MSP_INSN (swpbx, -3, 1, 0x1080, 0xffc0), 161 MSP_INSN (sxtx, -3, 1, 0x1180, 0xffc0), 162 163 /* MSP430X Address instructions - no extension word needed. 164 The insn_opnumb field is used to encode the nature of the 165 instruction for assembly and disassembly purposes. */ 166 MSP_INSN (calla, -1, 4, 0x1300, 0xff00), 167 168 MSP_INSN (popm, -1, 5, 0x1600, 0xfe00), 169 MSP_INSN (pushm, -1, 5, 0x1400, 0xfe00), 170 171 MSP_INSN (rrcm, -1, 6, 0x0040, 0xf3e0), 172 MSP_INSN (rram, -1, 6, 0x0140, 0xf3e0), 173 MSP_INSN (rlam, -1, 6, 0x0240, 0xf3e0), 174 MSP_INSN (rrum, -1, 6, 0x0340, 0xf3e0), 175 176 MSP_INSN (rrux, -1, 7, 0x0340, 0xffe0), /* Synthesized in terms of RRUM. */ 177 178 MSP_INSN (adda, -1, 8, 0x00a0, 0xf0b0), 179 MSP_INSN (cmpa, -1, 8, 0x0090, 0xf0b0), 180 MSP_INSN (suba, -1, 8, 0x00b0, 0xf0b0), 181 182 MSP_INSN (reta, -1, 9, 0x0110, 0xffff), 183 MSP_INSN (bra, -1, 9, 0x0000, 0xf0cf), 184 MSP_INSN (mova, -1, 9, 0x0000, 0xf080), 185 MSP_INSN (mova, -1, 9, 0x0080, 0xf0b0), 186 MSP_INSN (mova, -1, 9, 0x00c0, 0xf0f0), 187 188 /* Pseudo instruction to set the repeat field in the extension word. */ 189 MSP_INSN (rpt, -1, 10, 0x0000, 0x0000), 190 191 /* End of instruction set. */ 192 { NULL, 0, 0, 0, 0 } 193 }; 194 195 #endif 196
